How to Implement Error Handling in a VHDL T Flip-Flop Design?

[parasgupta6]

Problem Statement: (a) Write a T-flip-flop description with a clock (clk) and a t input. Toggling is done on the rising edge of (clk) when t is '1'. Include a generic parameter for the flip-flop delay, one for minimum pulse width on t, and one for the flip-flop identification number. The flip-flop should be able to report an error message (use assertion statements) if a glitch of less than the specified parameter is detected on its t input. The message should include the flip-flop identification number. (b) Write a generate statement for generating an unconstrained counter using t flip-flops of part a. Do a configuration declaration for binding the counter to its flip flop and specifying its generic values. (d) Write a test bench for testing the counter. Test for narrow input glitches and see if a warning message is generated.

 

[chroot]

We will not do your homework for you. If you need help, please show us your work, and explain where you're stuck.

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[parasgupta6]

I am not asking you to do my homework. I am facing problems with it.
I know the T Flip Flop design. tried using assert with it, but didn't help. i have no idea about identification no. and part (b)

 

[parasgupta6]

i have done dis much...but der are too many errors...pleasez remove the errors and post d correct answer


library ieee;
use ieee.std_logic_1164.all;

entity pbl is
generic ( n: integer; delay: time );
port ( t,clk : in std_logic;
q : out std_logic);
end pbl;

architecture tff of pbl is
signal data: std_logic;
begin
process(clk,t)
begin
if clk'event and clk = '1' then
if t'last_event < delay then
assert(t'last_event > delay)
report "input duration was less"
severity warning;
else
if t= '1' then
data <= not data;
end if;
end if;
end if;
q <= data;
end process;
end tff;



library ieee;
use ieee.std_logic_1164.all;

entity my_counter is
port(reset,clk:in std_logic;
have : out std_logic_vector(2 downto 0));
end my_counter;

architecture behav of my_counter is
component pbl
port(t,clk : in std_logic;
q : out std_logic);
end component;

signal enter_count : std_logic_vector(2 downto 0);

begin

enter_count <= "000" ;
if (clk'event and clk = '1' and reset='0' )

for i in 0 to 2 generate
if i = 0 generate
t_ff1 : pbl port map(t, clk , enter_count(i+1));
else
t_ff2 : pbl port map(q(i-1), clk, enter_count(i));
end if;
end generate;
end if;
end if;
have <= enter_count;
end behav;