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How to measure the mode of a FET

  1. Oct 17, 2015 #1
    1) When a FET is completely on, the voltage drop across the drain-source is ideally 0. This means that when completely on, [itex]V_{ds}<V_{gs}[/itex]. Why doesn't the FET go into ohmic/triode mode when [itex]V_{ds}[/itex] dips below [itex]V_{gs}[/itex] ?

    2) Why are we measuring these voltages relative to the source (for a standard n-channel fet)? What is it about the geometry of the semiconductor that makes the operation predictable by measuring the voltages relative to the source?

  2. jcsd
  3. Oct 17, 2015 #2
  4. Oct 18, 2015 #3
    An interesting read but I still have my question. Why doesn't the FET drop into ohmic mode when the voltage at the drain drops below the gate? If the FET is fully on, the voltage is being only slightly dropped over drain-source.
  5. Oct 18, 2015 #4


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    It IS in ohmic mode when Vds < Vgs-Vth
    For a given Vgs, as you increase the drain current the drain voltage increases "linearly" until it saturates.

    Your second question is too basic to answer. Do you understand how an enhancement mode FET works?
  6. Oct 18, 2015 #5
    No, I mean a FET that is in saturation mode. In saturation, Rds is very small (usually fractions of an ohm, lets say its 1 ohm), so if Vgs is at a normal value (say 5v) then the drain current would have to be 5A or more to have a drain voltage higher than the gate voltage. This is what has me confused.
  7. Oct 19, 2015 #6


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    In saturation Vds can be low or high since FET saturation is a current limit. In saturation a fet is a current source/sink. Don't compare it to the saturation of a bipolar transistor which is constant voltage.

    IN the saturation region you cannot increase the current for a given Vgs.

    The ohmic region is more analogous to the bipolar transistor's saturation region, when increased drain current causes smaller (ohmic in the FET case) Vds increases..
  8. Oct 19, 2015 #7
    Ideally, what is the voltage drop across the drain-source when the FET is a closed switch?
  9. Oct 19, 2015 #8


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    The Vds across the FET depends on Vgs and your definition of a closed switch (how much current is required).
    Look at the above chart until you are positive you understand it. I don't think you do. You think you understand, but you are missing it.

    Read this carefully: For a given Vgs (choose 5V) the voltage rises linearly with current until the channel cannot conduct more carriers. At 10 units of current it drops 1V. At 20 it drops 1.8V. When it reaches 21 units of current it is saturated. It can conduct no more current. If I increase the voltage from 4.5V to 10V, there is no increase in current because it is saturated. I can go to 100V and it will conduct no more current.

    You are confused about the very big difference between BJT saturation and FET saturation.

    Depending on Vgs, the FET can only conduct up to a maximum current, and no more. It is conducting its max current when it is saturated, and the voltage may be very high.

    If it is in the ohmic region (easily conducts the required current) then the voltage drop is small.

    Generally a FET is what we think of as a closed switch when it is ohmic.

    A FET conducts a fixed max current depending on Vgs. Below that current, it is ohmic.
  10. Oct 19, 2015 #9
    Ya I think I am confused, but I don't know where.

    Let's say [itex]V_{th}=1V[/itex]. Starting at [itex]V_g=0V[/itex], [itex]V_d=15V[/itex] and the FET is cutoff. Now we instantaneously increase [itex]V_g[/itex] to [itex]2V[/itex]. Then [itex]V_d=15-I_d R_d[/itex], but to calculate [itex]I_d[/itex] we need to know the mode of operation since we will have two different equations for the drain current. BUT to know the mode of operation we need to know the current through [itex]R_d[/itex] to find [itex]V_d[/itex].

    So essentially it looks like we need [itex]I_d[/itex] to calculate [itex]V_d[/itex] but we need [itex]V_d[/itex] to KNOW how to calculate [itex]I_d[/itex] (which equation).
  11. Oct 19, 2015 #10
    Actually I think I got it. So in my circuit above, in order to keep the FET in saturation, are you forced to choose the resistor value such that [itex](15 - I_{Dsat}R_D)>V_{GS}[/itex]?
  12. Oct 20, 2015 #11
    Ok, I understand now. I was confused because I kept reading that you almost always want to avoid the linear region, but the linear region they were talking about was when the FET is in the process of turning on. That's why...

    ...didn't get through my thick skull the first time I read it. I'm sorry, but what a terrible choice of words; bjt saturation is different from fet saturation, calling the region where the fet is turning on "the linear region" when you already have a mode of operation called the linear region, etc. What are these engineers doing? haha

    Anyways, thanks for the help!
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