Integration limitations to a SiC microprocessor

[ZeroFunGame]

TL;DR

There has been a demonstration of SiC BJT ACDs, and SiC JFET SRAM. What would be the major limitations associated with higher forms of integration for SiC? For example, a 1billion transistor CPU based on SiC?

There has been a demonstration of SiC BJT ADCs, and SiC JFET SRAM. What would be the major limitations associated with higher forms of integration for SiC? For example, a 1billion transistor CPU based on SiC?

 

[berkeman]

Links please?

 

[ZeroFunGame]

10 bit SAR ADC using SiC BJT: https://kth.diva-portal.org/smash/get/diva2:1138345/FULLTEXT02.pdf

SiC JFET RAM: https://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/20180003391.pdf

 

[trurle]

Summary: There has been a demonstration of SiC BJT ACDs, and SiC JFET SRAM. What would be the major limitations associated with higher forms of integration for SiC? For example, a 1billion transistor CPU based on SiC?

There has been a demonstration of SiC BJT ADCs, and SiC JFET SRAM. What would be the major limitations associated with higher forms of integration for SiC? For example, a 1billion transistor CPU based on SiC?

P-channel SiC MOSFET was developed only recently (in 2017). Previous models of integrated SiC chips have used N-channel MOSFETonly, and N-channel only architectures do limits integration to roughly 80386 levels (<1 mln. transistors), because of associated high power dissipation.
https://powerelectronicsworld.net/article/101899/Making_A_Debut_The_P-type_SiC_MOSFET/feature
I think it would take several years before SiC CMOS technology will be really available on market though.

 

[ZeroFunGame]

P-channel SiC MOSFET was developed only recently (in 2017). Previous models of integrated SiC chips have used N-channel MOSFETonly, and N-channel only architectures do limits integration to roughly 80386 levels (<1 mln. transistors), because of associated high power dissipation.
https://powerelectronicsworld.net/article/101899/Making_A_Debut_The_P-type_SiC_MOSFET/feature

Thanks trurle! Very insightful! I was curious how the 80386 levels was concluded? I wondering because, if power/efficiency was not a design spec, then would it follow that >1 mln. transistor systems are achievable? Or are there fundamental limitations to n-type VLSI?

 

[ZeroFunGame]

P-channel SiC MOSFET was developed only recently (in 2017).

Also, I'm not sure SiC PMOS was only developed in 2017 -- here's a SiC CMOS demonstration in 1997

https://ieeexplore.ieee.org/abstract/document/568759

 

[phyzguy]

Summary: There has been a demonstration of SiC BJT ACDs, and SiC JFET SRAM. What would be the major limitations associated with higher forms of integration for SiC? For example, a 1billion transistor CPU based on SiC?

There has been a demonstration of SiC BJT ADCs, and SiC JFET SRAM. What would be the major limitations associated with higher forms of integration for SiC? For example, a 1billion transistor CPU based on SiC?

All highly integrated ICs today are based on CMOS MOSFETs, not BJTs or JFETs. As @trurle pointed out, until we have good NMOS and PMOS transistors in SiC, you will not see the kind of "100's of million transistor +" levels of integration that you are used to with Si CMOS. Even then, there are probably many processing techniques that have been developed to work with Si that, for one reason or another, don't work with SiC. It will take time to develop the new methods. And I'm not sure what the financial motivation is. It's true there are markets (high-temperature, for example) where SiC outperforms Si. But is this more than a niche market? Is the market large enough to give the developers incentive to switch from Si?

 

[ZeroFunGame]

As @trurle pointed out, until we have good NMOS and PMOS transistors in SiC, you will not see the kind of "100's of million transistor +" levels of integration that you are used to with Si CMOS.

Thanks phyzguy! "Good" appears subjective here. Would it be possible to quantify the minimum mobility needed for NMOS and PMOS needed for "100's of million transistor +" levels of integration?

I appreciate all the feedback! Hoping for data/publications/references to go along with the posts. As @berkeman pointed out:

Links please?

 

[trurle]

Also, I'm not sure SiC PMOS was only developed in 2017 -- here's a SiC CMOS demonstration in 1997

https://ieeexplore.ieee.org/abstract/document/568759

I am not even sure the leaflet of 2017 can be counted as "useful SiC CMOS process", not even speaking of research paper in 1997. Current digikey.com inventory of p-channel SiC MOSFETs is 3 positions with 1 device variety (while over a thousand of N-channel SiC MOSFETs).

 

[trurle]

Thanks trurle! Very insightful! I was curious how the 80386 levels was concluded? I wondering because, if power/efficiency was not a design spec, then would it follow that >1 mln. transistor systems are achievable? Or are there fundamental limitations to n-type VLSI?

Because N-type VLSI have a significant stand-by power independent of transistor width (and reverse proportional to gate length), Si NMOS process did run in thermal troubles as soon as each transistor active area (channel+drain+source) was shrinked to roughly 4um2 size. With practical transistors active area density 15% in digital chips, 1mln transistors chip would be 5x5mm size, which is close to maximally practical with respect to cost.

 

[ZeroFunGame]

I am not even sure the leaflet of 2017 can be counted as "useful SiC CMOS process", not even speaking of research paper in 1997. Current digikey.com inventory of p-channel SiC MOSFETs is 3 positions with 1 device variety (while over a thousand of N-channel SiC MOSFETs).

Thanks trurle! Certainly there are already SiC CMOS foundaries, for example KTH in Sweden and Fraunhofer in Germany. Sure, they may not be commercial products, but there's significant R&D (like the early days of Si) and it will not be long before they enter into main-stream.

 

[ZeroFunGame]

which is close to maximally practical with respect to cost.

This assumes the application is for a consumer product. There are particular high-mix low-volume markets that cost is not an issue. The original question steers away from economics, but focuses primarily on the technology enablement and fundamental physical limitations