Is Propagation delay from 1 to 0 the same as that from 0 to 1?

[christang_1023]

Homework Statement: There are the propagation delays from High to Low and from Low to High, and I wonder if they are equal?
Homework Equations: That is
$$ t_{PLH}=t_{PHL}$$

I suppose they should be equal.

 

[phinds]

I suppose they should be equal.

I don't, with a caveat. I think it may depend on the characteristics of the rest of the circuit.

Here's my thinking. Take the very simple case of a PNP transistor with a pull-up resistor on the collector. When you put a high voltage into the base resistor, this creates an active path from the collector to ground through the emitter, and thus the change is, absent anything weird in the remainder of the circuit, going to be function of the characteristics of the transistor, not the remainder of the circuit. However, when you release the voltage on the base resistor, you have shut off the active path to ground and created a passive path back to the supply voltage and thus the response will depend more strongly on the remainder of the circuit because of possible difference between the actions of an active path and a passive path.

 

[sophiecentaur]

I don't, with a caveat. I think it may depend on the characteristics of the rest of the circuit.

Here's my thinking. Take the very simple case of a PNP transistor with a pull-up resistor on the collector. When you put a high voltage into the base resistor, this creates an active path from the collector to ground through the emitter, and thus the change is, absent anything weird in the remainder of the circuit, going to be function of the characteristics of the transistor, not the remainder of the circuit. However, when you release the voltage on the base resistor, you have shut off the active path to ground and created a passive path back to the supply voltage and thus the response will depend more strongly on the remainder of the circuit because of possible difference between the actions of an active path and a passive path.

What you seem to be suggesting is that the pulse shape is not symmetrical with an asymmetrical logic gate. I agree and this means that the two (on/off) time constants can be different. When a long signal path needs to be catered for, a proper symmetrical 'driver' circuit can improve matters. (Also a good termination at the receive end can help.)

 

[berkeman]

Homework Statement: There are the propagation delays from High to Low and from Low to High, and I wonder if they are equal?
Homework Equations: That is
$$ t_{PLH}=t_{PHL}$$

I suppose they should be equal.

It depends on the logic family. There are assymmetries between the pullup and pulldown transistors at gate outputs and also in the propagation paths inside the gates, so in general the two propagation delays will not be equal.

You can check this by just looking at the datasheets for some typical logic gates. For CMOS gates, the P-channel FETs will be slower and weaker than the N-channel FETs if they are the same size, but the gate manufacturer may try to do some things to make them more equal (different sizes, etc.).

Have a look at a 74S00 datasheet and schematic. You can see that the pulldown transistor at the output stage will probably generate sharper pulldown edges versus the pullup transistor section, yet tPLH is a bit faster overall in the datasheet. The logic levels are also different for TTL versus CMOS gates, so that also enters into the slight differences between the tPLH and tPHL times.

http://materias.fi.uba.ar/6619/DM74S00.pdf

https://www.nutsvolts.com/magazine/article/understanding_digital_logic_ics_part_2

 

[DaveE]

Recognize that a question like this is nearly meaningless without a description of the system you are interested in. They could be equal, or not. I have no idea.

 

[eq1]

I don't, with a caveat. I think it may depend on the characteristics of the rest of the circuit.

It absolutely does.

For example, why assume the bit is encoded single ended. It could be differential and if it’s differential it’s a lot easier to make it symmetric.

 

[Baluncore]

Propagation Delay, or Transition Time?

There are differences in the high-to-low and low-to-high transition times of outputs. Most logic technologies have asymmetric structures, so are expected to have different rise and fall times. Asymmetric examples are RTL, I²L, DTL, TTL, and hybrids with asymmetric thresholds like the 74HCT series. Some appear to be symmetrical, but are really not, such as CMOS which uses N and P channel MOSFETs with different characteristics. Examples are CD4000 and 74HC series.
Only truly differential systems such as some series of ECL are balanced with respect to transition time.

The propagation time through a gate is usually more variable than the output transition time as it is determined by the internal logic topology of the gate. More complex logic blocks will have greater variations in propagation delay. Propagation delay will depend primarily on which input causes the output to change, and how many stages there are between input and output.

But it really does not matter that the transition times or propagation delays are different. Clocked systems latch data or advance state on either the positive or negative edge, rarely both. The designer must allow for worst case timing for the data being clocked through the system.