Pullup Resistors & TTL Gates: Reducing Delay and Noise

Click For Summary

Discussion Overview

The discussion revolves around the use of pullup resistors with TTL gates, particularly regarding the implications of floating inputs, propagation delay, and noise susceptibility. Participants explore the necessity of pullup resistors in various scenarios, including connections to open-collector outputs and the treatment of unused inputs across different logic families.

Discussion Character

  • Technical explanation
  • Debate/contested
  • Conceptual clarification

Main Points Raised

  • Some participants assert that a "high" input of a TTL gate should not be left floating and should be connected to +Vcc through a pullup resistor to reduce propagation delay and noise capture.
  • Others argue that unused inputs in any logic family should not be left floating due to power consumption and noise concerns, suggesting that pullup resistors are necessary only when connecting to an open-collector output.
  • One participant notes that floating inputs can switch states rapidly due to noise, leading to power waste from charging or discharging on-chip capacitance.
  • There is a viewpoint that while using pullup resistors is a good practice, it is less critical for TTL compared to other logic families like CMOS, where floating inputs are particularly problematic.
  • Another participant emphasizes that how an input is tied depends on its logical function, stating that unused inputs of AND/NAND gates should be tied high, while those of OR/NOR gates should be tied low.
  • A later reply clarifies that the directional preference for tying unused inputs relates to preserving logical functions, although it is noted that this is not tied to the electrical behavior of CMOS transistors.

Areas of Agreement / Disagreement

Participants express differing views on the necessity and implications of using pullup resistors, particularly in relation to TTL versus CMOS logic families. The discussion remains unresolved regarding the best practices for handling unused inputs and the importance of pullup resistors in various contexts.

Contextual Notes

There are limitations in the discussion regarding assumptions about the electrical behavior of different logic families and the specific conditions under which pullup resistors should be used. The conversation does not resolve the nuances of these technical claims.

antonantal
Messages
242
Reaction score
21
Is it true that a "high" input of a TTL gate shouldn't be left floating but instead connected to +Vcc through a pullup resistor because this way the propagation delay time is reduced and less noise is captured?
If that's true, should a pullup resistor be used when connecting the input of a TTL gate to the output of an open-collector driving gate?
 
  • Like
Likes   Reactions: curious_mind
Engineering news on Phys.org
Unused inputs on basically any logic family should not be left floating. The issues has to do with power consumption and noise. If the input is used (connected to some other gate's output), then a pullup resistor is only needed if the output driving it is open collector.
 
Floating inputs have the potential of rapidly (and randomly) switching from the high to low states due to noise. Everytime they flip, all the on-chip capacitance they're driving has to be charged or discharged, wasting power.

- Warren
 
I see. Thanks for your answers.
 
It's a good practice, but this is mostly a non issue in the case of TTL.
However, for other logic familys, like CMOS, it is extremely important to not leave inputs flaoting.
 
NoTime said:
It's a good practice, but this is mostly a non issue in the case of TTL.
However, for other logic familys, like CMOS, it is extremely important to not leave inputs flaoting.

Of course, who actually uses BJTs for digital output drivers anymore? Anyone at all? Any digital device designed in the last couple of decades is going to have CMOS logic.

- Warren
 
One little additional point. How an input is "tied" also depends on what that input is to do logically. "Unused" doesn't mean that the input isn't doing anything --- all inputs will do something whether we ignore them or not. Thus, an unused input to an AND/NAND must be tied (through a pullup) to Vcc (a "1" value), and likewise an unused OR/NOR input must be tied to Ground.

KM
 
Kenneth Mann said:
One little additional point. How an input is "tied" also depends on what that input is to do logically. "Unused" doesn't mean that the input isn't doing anything --- all inputs will do something whether we ignore them or not. Thus, an unused input to an AND/NAND must be tied (through a pullup) to Vcc (a "1" value), and likewise an unused OR/NOR input must be tied to Ground.

KM
Interesting. I hadn't heard that before. Why the directional preference for the different function gates?
 
berkeman,

He's simply saying that if you have a 3-input AND gate and want to leave one of its inputs unused, you need to tie it high to preserve the logical AND function between the remaining two inputs. Likewise, if you want to leave an input of an OR gate unused, you need to tie it low.

Neither of these observations have anything to do with the electrical behavior of the CMOS transistors used in making the gate, and are therefore pretty much irrelevant.

- Warren
 
  • #10
OH! Now I get what he was saying. I was thinking unused gate, not just unused individual inputs. That clears it up. Thanks!
 

Similar threads

Replies
80
Views
5K
  • · Replies 29 ·
Replies
29
Views
4K
Replies
2
Views
3K
  • · Replies 4 ·
Replies
4
Views
2K
Replies
2
Views
8K
  • · Replies 7 ·
Replies
7
Views
5K
Replies
9
Views
4K
Replies
17
Views
11K
Replies
4
Views
2K
  • · Replies 26 ·
Replies
26
Views
17K