Logic gate question -- Tying both inputs of a gate together

[akaliuseheal]

Hello,
I don't know much about logic gates and how they work.
I was wondering if this (Image) can work. (Is something like this possible?)

The idea is that if we have logic 1, AND gate gives 1 while NOR gives 0. And vice versa.

 

[.Scott]

It will work.
Tying both inputs of an And/Or/Nor gate is often used for signal conditioning - or more rarely, to introduce a 1-gate delay in the signal.

 

[berkeman]

Quiz Question for @akaliuseheal -- If the input to your circuit is first a 1 and then a 0 ("1/0"), can you tell us what the output of each of the two gates will be?

 

[akaliuseheal]

Quiz Question for @akaliuseheal -- If the input to your circuit is first a 1 and then a 0 ("1/0"), can you tell us what the output of each of the two gates will be?

Input = 1
AND 1 | NOR 0

Input = 0
AND 0 | NOR 1

 

[akaliuseheal]

It will work.
Tying both inputs of an And/Or/Nor gate is often used for signal conditioning - or more rarely, to introduce a 1-gate delay in the signal.

Thanks.

 

[akaliuseheal]

Unrelated to the topic, is there any way for me to mark this thread as SOLVED since it is.

 

[berkeman]

The Solved checkbox is only available in the Homework Help forums, not in the technical forums. I can add it to your thread title if you like.

EDIT -- Thread title edited.

 

[Averagesupernova]

A wise engineer once told me to be careful when configuring gate in the manner as shown above. Worth mentioning here even though it would not apply to an AND gate. In some cases of using a NAND gate as an inverter you would want to tie the input signal to just one input on the gate. Quiz question: Can anyone answer why?

 

[TylerV]

A wise engineer once told me to be careful when configuring gate in the manner as shown above. Worth mentioning here even though it would not apply to an AND gate. In some cases of using a NAND gate as an inverter you would want to tie the input signal to just one input on the gate. Quiz question: Can anyone answer why?

I would love to know the answer to this, would it not be easier to just tie the inputs together? If you only connected one input, the other would have to go to a high, which complicates the circuit.

 

[berkeman]

I would love to know the answer to this, would it not be easier to just tie the inputs together? If you only connected one input, the other would have to go to a high, which complicates the circuit.

Welcome to the PF.

Can you think of some reasons for only connecting the signal to one of the two inputs of the NAND gate? I can think of at least two, but I don't know if they are what @Averagesupernova was thinking of...

 

[TylerV]

Welcome to the PF.

Can you think of some reasons for only connecting the signal to one of the two inputs of the NAND gate? I can think of at least two, but I don't know if they are what @Averagesupernova was thinking of...

I would say speed is an issue I would be worried about, and with only one input,the other input will be a constant and there would be no worry if the two values reach the gate at the same time or not

 

[berkeman]

I wasn't thinking along those lines... Any other thoughts? What can be typical problem issues in digital logic design?

 

[TylerV]

I wasn't thinking along those lines... Any other thoughts? What can be typical problem issues in digital logic design?

The only other frequent problem I deal with is noise/grey area, but I don't see how that is applicable here. Tell me what you think is the problem with it?

 

[berkeman]

Well, the two issues I see are that when you make 2 connections to the gate, you are doubling the power required to switch the signal (for no real gain), and the increased loading on the line will reduce your fan-out for that signal by 1. That may not matter if the signal is not used anyplace else, but if you are close to the fan-out limit already for that signal, wasting one connection is not good.

@Averagesupernova may have other issues in mind...

 

[Averagesupernova]

Sorry it took me a bit to get back here. I don't recall the exact topology of the circuit that the gate was in but it has to do with inconsistencies between individual gate inputs. Besides loading effects of more than one gate input, why use more than one input when it is not necessary? If there is a significant slew rate on the signal driving the input(s) at least with one gate there is only one input to move around and change timing over temperature range.
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So with that said, can anyone give me a reason why gate inputs get tied together like this instead of just tying one input high when making a NOT gate out of an NAND gate? I have my ideas and in some cases it is justified to tie them together. I promise I won't leave you hanging.

 

[TylerV]

So with that said, can anyone give me a reason why gate inputs get tied together like this instead of just tying one input high when making a NOT gate out of an NAND gate? I have my ideas and in some cases it is justified to tie them together. I promise I won't leave you hanging.

I would tie them together if I was designing a pcb with many parts. This is because I do not want to have a trace going all the way to my V+ when instead I could just have the two inputs tied at the pads. At least that is my reasoning behind it, tying them would just simplify my circuit and allow me to have more space on my board for other components/traces.

 

[Averagesupernova]

'All the way to V+' isn't that far but it was the reason I was thinking. It is only as far as a different pin on the device. But, nonetheless it may save a designer a via or two on the PCB, etc. Often optimising which gate is used on a device can solve this.
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I once worked for a company who's CAD system was so unreliable that whichever change to the design was least likely to crash the system is the one which was chosen.