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Tri-state logic: High impedance as an input to a logic gate

  1. Apr 16, 2013 #1
    So I am well familiar with how bi-state logic (with 0s and 1s) works in gates. 0+0=0; 0+1=1+0=1+1=1 etc.

    What happens if an input to a gate is neither 0 nor 1, but has an high-impedance value? Will it disable the logic gate from working? Will the logic gate simply ignore that input? Anyone have any clues? Perhaps it depends on what series chip one is using?

    Really appreciate it! Thanks!

  2. jcsd
  3. Apr 16, 2013 #2

    jim hardy

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    Gold Member


    Look at a TTL chip schematic. It pulls its input high through a resistor on base, emitter goes to input pin..
    One asserts input by sinking I think 1.6ma of emitter current.
    So it'll probably interpret open circuit as logic high.
    Trouble is, an open inputs is susceptible to noise - the pcb track connected to it is an antenna so you get errors.
    Floating inputs are troublemakers.
  4. Apr 16, 2013 #3


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    Staff: Mentor

    As Jim says, floating logic inputs are a bad thing. In addition to picking up noise and possibly oscillating, when the input to a CMOS gate floats near the middle voltage between Vdd and Vss, the gate output circuit can go into a conducting state, where both the pullup and pulldown transistors are ON. That increases the current consumption of the logic gate by quite a bit.

    So the design rule is generally that you do not want to leave any logic inputs floating. Either tie them off with a pullup or pulldown resistor, or configure them as outputs (like the IOs of a microcontroller).
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