LT spice result analysis, Capacitance Multiplier vs RC filter circuit

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brainbaby
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Hi friends,

I have simulated two circuits, one is an RC filter and other is a Capacitance multiplier.
My aim of experiment is to validate a decrease in Iout (load current) of CM circuit as compared to load current in RC filter circuit.

Theoretically,
Iout (CM circuit) < Iout (RC filter)
Vp-p (CM circuit) < Vp-p (RC filter)

My results:
1.RC filter
Vout (dc) = 0.0458716 ( .op 300ms)
Iout (dc) = 0.00458716

Vout (ac) = 43.7 ~ 48 mV (.tran 300ms)
Iout (ac) = 4.80 ~ 4.37 mA

Vp-p (ripple) = 0.00437018 (.meas)

2.CM circuit

Vout (dc) = 0.323751
Iout (dc) = 0.0323751
Vout (ac) = 322 ~ 327 mV
Iout (ac) = 32.65 ~ 32.15 ma

Vp-p (ripple) = 0.00521016 (.meas)

From the above results its quite clear that implementing CM circuit causes Iout to increase which particularly against the aim of the CM circuit. As the CM circuit works by decreasing the load current which according to load POV can be visualised as increase in capacitance.
We can also see the peak to peak ripple voltage in both the circuits, Vp-p for CM circuit should be less than Vp-p ripple of an RC filter, but again the simulations results are quite opposite.

What's wrong here??

LTspice schematic of a transistor capacitance multiplier: input source V1 with ripple, Q1 2N4401 NPN emitter follower, R1 4k and R3 1.26k base divider, C1 100µ, load R2 10 ohm, with .tran 300ms and .meas Vpeak directives.


LTspice schematic of an RC filter: source V1 (SINE(0 0.25 50), AC 1) drives VIN through R1 1.08k to VOUT, with C1 100u shunting to ground and R2 10 as the load; V2 is a 5 V source in series below ground, with directives .op 300ms, ;tran 300ms and .meas tran Vpeak pp V(vout).
 
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Is this not just an extension of your previous thread ?
https://www.physicsforums.com/threads/measuring-ripple-reduction-in-ltspice.1001493/

Why make it so complex ? You have too many places in the circuit to hide difficulties and differences. If the two circuits were merged into one_file.asc, you could compare the results directly.

1. Why specify two voltage sources in series when the DC offset can be specified in one ?

2. What is so special about the detailed 2N4401 model ? Why can you not use a traditional 2N2222 that is included in every version of LTspice ?

3. When 50 Hz is “full wave” rectified, the ripple approximates a saw-tooth with a fundamental frequency of 100 Hz. By specifying a 50 Hz sinewave, you are analysing a frequency component that does not exist, while ignoring every significant harmonic.
 
Because the CM circuit is buffered with the emitter follower, it has a higher output voltage and therefore a higher output current when operating into the same load resistance. The ripple in the CM circuit is also less because load current is not being drawn from the capacitor.

I have given the input waveform a 100 Hz saw-tooth.
Also, offset the DC of the CM voltage in the plot to get better resolution.

LTspice schematic comparing a capacitance multiplier (transistor Q1 2N2222 with R1, R3, R2, C1 100u) and an RC filter (R4 1.08k, C2 100u, R5 10), fed by a 5 VDC pulse source with 100 Hz saw ripple, with .meas directives and measured ripple and efficiency values printed below.

LTspice plot of two voltage waveforms over 0 to 40 ms, both ripple around 44 to 47 mV: a green trace labelled V(rc) with sharper peaks and a grey trace labelled V(cm)-0.251 with smaller ripple.
 
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