Makefile in Unix environment: help!

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NEVER MIND! I finally found a good reference explaining all of this. Sorry for the wasted bandwidth!


I have this makefile I am trying to understand.

It goes like this:

COMP = ifort
FLAGS = -autodouble etc...
GLOBALS = a bunch of .o files....

glue: gluon_operators.o
$(COMP) $(FLAGS) -o main_program *.o

gluon_operators.o: gluon_operators.f90 loop_functions.o $(GLOBALS)
$(COMP) $(FLAGS) -c gluon_operators.f90

and so on...

I understand that this is compiling stuff using the Fortran compiler with some flags.

What I am confused about are the lines with a ":", for example

glue: gluon_operators.o

I have no idea what this line does.
Also, the line

gluon_operators.o: gluon_operators.f90 loop_functions.o $(GLOBALS)

is a mystery to me. What does the ":" do?

Also, I don't understand the line with main_program. It seems to me that the -o says to output the result of the compilation to main_program, but there does not seem to be anything compiled in the first place ?! I would have expected $(COMP) $(FLAGS) program.f90 -o main_program or something similar.

Also, what does the "*.o" mean at the end of that same line? It says something about all files ending with .o but I don't quite understand the whole line. Maybe it says that anything that will be compiled next must
put together in the file main_program??

I would really appreciate help!

Last edited:
For others who have the same question, I found this reference --
Defining Rules in Makefile

We will now learn the rules for Makefile.

The general syntax of a Makefile target rule is −
target [target...] : [dependent ....]
[ command ...]

In the above code, the arguments in brackets are optional and ellipsis means one or more. Here, note that the tab to preface each command is required.

A simple example is given below where you define a rule to make your target hello from three other files.
hello: main.o factorial.o hello.o
$(CC) main.o factorial.o hello.o -o hello

NOTE − In this example, you would have to give rules to make all object files from the source files.

The semantics is very simple. When you say "make target", the make finds the target rule that applies; and, if any of the dependents are newer than the target, make executes the commands one at a time (after macro substitution). If any dependents have to be made, that happens first (so you have a recursion).

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