Detecting Logic State of 6 in Binary with Decoder Glitches

[sandy.bridge]

Hello all,
I have a lab this afternoon that I was going over to ensure I was prepared for it. However, I am not entirely sure about the last part of the lab. Any help or reassurance is appreciated!

Decoder Glitches- Use a 3 input AND function to detect the logic state corresponding to "6" in binary (Q8=1, Q4=1 and Q2=0). Use a logic analyzer to display the expected output and the very brief "glitch" that occurs at the beginning of the zero state.

I'm looking for reassurance as to the first part. I have decided to use a frequency divider utilizing D flip flops, an inverter and an AND gate. Attached is my photo. The AND gate outputs 1 when Q8Q4Q2'=110, which is six.

Thanks!

 

[Tom.G]

The three flip flops are connected as a 'Ripple Counter.'

The third flop will not change state until after the second on has, and the second one will not change state until after the first one has.

At the maximum count of 7, the next state is 0. However the first flop toggles to 0 before the others do, which is decoded as 110b, or 6. That is the source of the 'glitch' just before the 0 state.