Solving ModelSim XE III 6.2g Digital Circuit Design Issue

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AI Thread Summary
The user faced issues while running a testbench simulation in ModelSim XE III 6.2g after designing a digital circuit. The errors indicated that a formal port "i" in the VHDL code had no actual associated with it, leading to a compilation failure. The user initially sought help to resolve the problem, but later identified their mistake independently. The discussion highlights common challenges in VHDL simulation and the importance of correctly associating ports. Ultimately, the user resolved the issue on their own.
soul
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For the digital circuit design lesson we have to install xilinx and modelsim. After I designed the circuit and run the testbench simulation, I encountered a problem.

# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl
# do intro_tb.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE III vcom 6.2g Compiler 2007.02 Feb 22 2007
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package vcomponents
# -- Compiling entity intro
# -- Compiling architecture behavioral of intro
# ** Error: intro.vhf(90): (vcom-1035) Formal port "i" has no actual associated with it.
# ** Error: intro.vhf(109): VHDL Compiler exiting
# ** Error: C:/Modeltech_xe_starter/win32xoem/vcom failed.
# Error in macro ./intro_tb.fdo line 5
# C:/Modeltech_xe_starter/win32xoem/vcom failed.
# while executing
# "vcom -93 -explicit intro.vhf"

The bold lines were written with red. I do not how I can fix this problem. Can anyone help me?
 
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Ok. I found my mistake. Sorry for mess.
 

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