Need help to design a computer architecture

[udaymach]

Hi Fnz,
I have to design a barrel processor ..for which i have to take a simple processor and have to make changes in that existing architecture design such that we have to add a thread switch unit into the design and the threads had to switched after executing one instruction from each thread. Its more or like fine grained multithreading.
Can anyone please help me out how to make changes in the existing simple cpu design to bring out the barrel architecture.



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Thanks,
UDAY

 

[berkeman]

Hi Fnz,
I have to design a barrel processor ..for which i have to take a simple processor and have to make changes in that existing architecture design such that we have to add a thread switch unit into the design and the threads had to switched after executing one instruction from each thread. Its more or like fine grained multithreading.
Can anyone please help me out how to make changes in the existing simple cpu design to bring out the barrel architecture.



-
Thanks,
UDAY

What have you tried so far? What starting uP architecture are you thinking of starting with? What representation are you going to use for the project (block diagram, schematic, Verilog, etc.)?

 

[udaymach]

I have taken a simple 16-bit microprocessor (figure given in the attached file)and then i have to alter this architecture based on the below specification.

Just if i consider simple instructions for the processor that is enough.

The processor has to execute one instruction from each thread at a time for all threads upto N threads. I need to design the architecture for the Barrel processor and has to implement the processor on a FPGA by using VHDL.

So, I have to take a basic architecture of any of the processor and have to modify it such that the processor has N - number of PC,SP,SR,Thread IDs,etc. for each thread. I have to cycle all these registers of each thread at their turn executing only one instruction at a time.

For example Thread -1 is taken and all its corresponding CPU registers are loaded, then one instruction from this thread is executed. Then again Thread -2 is taken and all its CPU registers are loaded, then one instruction from this thread is executed, etc. upto N threads and again its cycled from the first.

Example:
Thread -1 ACC Ro-Rn PC SP Thread ID Flags Thread-status(En/Disable)
Thread -2 ACC Ro-Rn PC SP Thread ID Flags Thread-status(En/Disable)
Thread -3 ACC Ro-Rn PC SP Thread ID Flags Thread-status(En/Disable)

So, I have to design an architecture first and then i have to code in VHDL.

Can you please help me sir.