What is the Depletion Region in NMOSFET Transistors?

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SUMMARY

The depletion region in NMOSFET transistors decreases in length as the drain-source voltage (Uds) exceeds the gate-source voltage (Ugs), leading to an increase in current. This phenomenon occurs despite the apparent contradiction of a smaller conductive path, as the increase in current is a second-order effect, typically observed in saturation or constant current mode. Parasitic capacitances, particularly feedback capacitance (C_{gd}), negatively impact high-frequency performance by reducing input impedance and gain. Understanding these concepts is crucial for grasping the complexities of NMOSFET operation.

PREREQUISITES
  • Understanding of NMOSFET operation principles
  • Familiarity with voltage definitions: Uds and Ugs
  • Knowledge of parasitic capacitance and its effects
  • Basic grasp of first-order and second-order effects in electronics
NEXT STEPS
  • Study the effects of parasitic capacitance on NMOSFET performance
  • Learn about saturation and constant current modes in NMOSFETs
  • Investigate feedback capacitance (C_{gd}) in common source configurations
  • Explore advanced topics in semiconductor physics related to depletion regions
USEFUL FOR

Electrical engineers, semiconductor physicists, and students studying transistor behavior and high-frequency circuit design will benefit from this discussion.

Bassalisk
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Hello,

I am a bit confused about depletion region in NMOSFET transistor. It says here in my book, that when you increase Uds (drain source) above Ugs(gate source) that the current get higher. Ok, makes sense if nothing, from Ohms law. Simultaneously, the depletion region get smaller in length due to that voltage, that is bigger than drain source one(I can grasp with that concept too) but when I put that together, it doesn't make sense...

How can current get higher when the path through it can travel gets smaller(on the other end though).

I attached an relevant image.
 

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UPDATE: Relevant to this question: parasitic capacitance, I understand somewhat how it occurs. But why are they so bad? And why would one try to get rid of that capacitance?
 
Bassalisk said:
UPDATE: Relevant to this question: parasitic capacitance, I understand somewhat how it occurs. But why are they so bad? And why would one try to get rid of that capacitance?

Parasitic capacitances reduce the high frequency performance of the transistor. They shunt away both input current and output current and hence reduce both input impedance and gain at high frequencies. The worst of all is the feedback capacitance, for example C_{gd} (aka the reverse transfer capacitance C_{rss}) in the common source configuration. The voltage variation across this capacitance gets multiplied by the voltage gain of the circuit, and so in turn does it's determent on the high frequency performance.
 
Last edited:
RE your original question :
How can current get higher when the path through it can travel gets smaller(on the other end though).

You have to understand that this increase in current is a second order effect. Meaning that to a first order approximation the current actually remains constant (The very mode of which your question refers to is call either "saturation" or "constant current" mode.)

So sorry to give you the "run around" here, but to understand the more esoteric second order effect you must first understand the basic "first order" approximation. To understand why the current increases you must first understand why it remains (approx) constant.

So you probably should ask that question first.
 
Took me 2 weeks to swallow the transistor effect... countless hours of searching. I guess I will have to do with FETs the same...

Thanks for your help, I have a good start though.
 

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