Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

NOT logic at transistor/componet level

  1. Apr 22, 2015 #1
    Hello all,

    Reading this article
    http://www.allaboutcircuits.com/vol_4/chpt_3/2.html
    explaining NOT logic at component level.

    I'm not sure I understanding the arrow drawn in this figure: above sentence "This tells us that ..."
    04165.png

    Is the arrow depicted current? If so, would that make passing the 5 V on the right as a "lost" of 5 V?
    Why Q3 was not included in this picture?

    Initial diagram:
    04074.png
     
    Last edited: Apr 22, 2015
  2. jcsd
  3. Apr 22, 2015 #2

    berkeman

    User Avatar

    Staff: Mentor

    Those arrows are crazy! Is he trying to plot electron flow? Bizzare...

    Ignoring everything after the first figure with the real schematic, do you see how that TTL inverter works? If not, just post the schematic pic and we can talk through it.
     
  4. Apr 22, 2015 #3
    to berkeman:
    No, I still don't understand, the schematic that is. That is weird if they want to bring up the electron flows direction.

    quick question:
    a) A diode in reverse bias is treated as an open?
    b) No voltage to the base of transistor is open at collector node?
     
  5. Apr 22, 2015 #4

    phinds

    User Avatar
    Gold Member
    2016 Award

    yes and yes
     
  6. Apr 22, 2015 #5
    @ the initial diagram:
    1) where the box with "0 V", why is that zero volt, should that be Vcc?
    2) can current travel from Vcc through R1 out of Q1 collector and into Q2 base? I thought current through transistor is unidirectional, from collector to emitter.
     
    Last edited: Apr 22, 2015
  7. Apr 23, 2015 #6

    NascentOxygen

    User Avatar

    Staff: Mentor

    The box apparently represents a multimeter; it is recording 0v between the base (connected directly to Vcc) and the Vcc bus. Let's call that box a DVM. :smile:

    Q3 is not involved here because it takes no part when input is HIGH. In this state, Q3 is deprived of base drive so Q3 is off.

    Yes, current flows wherever KVL says it can. :smile:

    B-C is a PN junction, just like a diode, so if it's forward biased it will conduct. When a transistor is used as a linear amplifier then B-C junction is kept reverse-biased, but in digital circuits the transistor characteristics can be exploited even more creatively. :wink:
     
  8. Apr 23, 2015 #7
    HI, first you must know that allaboutcircuits textbook use a electron flow not conventional flow.
    http://www.allaboutcircuits.com/vol_1/chpt_1/7.html

    And this is why the arrows in the diagram pointing in the opposite direction.
    Next notice that Q1 is a NPN transistor and his emitter is connected to Vcc. The base is also pull up to Vcc via R1 resistor. Therefore the base-emitter junction is reversed biased. So in normal situation Q1will be in cut-off region. But in this case Q1 collector is directly connected to Q2 base. And this change the situation completely.Can we find a closed path for Q1 base current from Vcc to GND?
    Yes we can. The base current can flow from Vcc--->R1--->Q1 Base -collector junction---->Q2 Base-emitter junction--->GND. Notice that Q1 base collector junction is now forward biased, and the is why the current can flow.
    So in this scenario Q1 is working in inverse mode also know as a reverse active region.
    Please notice that Q2 is in saturation region due to Q1 base-collector current. So what is happening here is that the current through R2 splits between Q1 collector current and the Q3 base current. The more current that is allowed to go through Q2 transistor ( Q2 in saturation), the less current that will go into the Q3 base.
    So Q2 simply steals all the Q3 base current ans this is why Q3 is cut-off.
     
    Last edited: Apr 23, 2015
  9. Apr 24, 2015 #8

    cnh1995

    User Avatar
    Homework Helper

    When input is 1 (Vcc), Q1(B-C),Q2(B-E) and Q4(B-E) act as forward biased diodes. Since BE junction of Q2 is forward biased, CE voltage will drop to a very small arrow-10x10.png value (equivalent to logic 0). Thus, voltage at the base of Q3 is also 0. So,Q3 is open circuited along with the D2 diode. That means base and collector of Q4 are at the same potential ,approximately 0.7 volts w.r.t ground, equivalent to logic 0. So, output CE voltage is low.
    When input is 0, Q1 will conduct, this will pull down voltage level at the base of Q2, turning it off. So, voltage at collector of Q2 will be high (logic 1). Meanwhile, Q2 being off, base of Q4 will be pulled down to ground potential. So, Q4 will be off. Vcc will reach to collector of Q4 through forward biased Q3 and D2. So,CE voltage of Q4 is Vcc i.e logic 1.
    If my understanding is right, I don't understand the purpose of D1 and D2 diodes, because without them too, the circuit will work as above. Am I missing something?
     
    Last edited: Apr 24, 2015
  10. Apr 24, 2015 #9
    D1 is just a protection diode.
    D2 diode has a very important task. But first let as check the situation when input is "high" (1).
    What is the voltage level at Q3 base?? Are you sure that this voltage is 0 ?
    Q3 base voltage must be equal to VbeQ4 plus Q2 saturation voltage.
    Vb3 = Vbe4 + Vce2sat = 0.6V + 0.2V = 0.8V . You are surprised ? How can Q3 be OFF if Q3 base voltage is 0.8V ??
    For sure without D2 diode Q3 transistor would have been turned on.
    And this is why designers add D2 into the circuit. To make sure that Q3 will be OFF when Q2 is saturated.
     
  11. Apr 24, 2015 #10

    cnh1995

    User Avatar
    Homework Helper

    Yeah..But if D2 weren't there, Q3 would turn on and conduct. But Q4 is already on with Vbe4=0.6 volts.That means collector current of Q4 will now pass through D2 and Q3,and a little base current through Q4 base. Still the output Vce4sat would be small enough (about 0.2V) i.e. logic 0.
     
    Last edited: Apr 24, 2015
  12. Apr 24, 2015 #11

    NascentOxygen

    User Avatar

    Staff: Mentor

    And that will be a waste of current, it achieves nothing useful and reduces the fan-out of Q4. We'd like all of the current through Q4 to be from the input stages of the gates that Q4 drives to maximize this gate's fan-out.
     
  13. Apr 24, 2015 #12

    cnh1995

    User Avatar
    Homework Helper

    Okay..I am not familiar with the concept of fan-out you are talking about...Gotta study that:smile: Thanks a lot..
     
    Last edited: Apr 24, 2015
  14. Apr 24, 2015 #13
    Well yes, but by doing this you are wasting a lot of current. Also without the load we have Ic3 = Ic4 so Vce_sat voltage will also increase his value and this will decrease the noise margin
    http://www.allaboutcircuits.com/vol_4/chpt_3/10.html
    Also notice that now Q4 can sink much smaller current from the load because know Ic4 = Iload + Ic3 before Q4 starts leaving the saturation region.
     
  15. Apr 24, 2015 #14

    cnh1995

    User Avatar
    Homework Helper

    Got it..Thanks:smile:
     
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook




Similar Discussions: NOT logic at transistor/componet level
  1. Transistor ? (Replies: 2)

  2. Transistor biasing (Replies: 11)

Loading...