PWM Controller period and duty cycle questions

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SUMMARY

This discussion focuses on the behavior of a PWM controller utilizing a 555 timer IC. It establishes that increasing the potentiometer (POT) resistance results in a decreased duty cycle due to longer switch closure times. Additionally, when the source voltage is increased while maintaining constant POT resistance, the period decreases while the duty cycle remains constant, indicating an increase in switching frequency. The interaction between supply voltage and the 555 timer's charging and discharging phases is crucial for understanding these dynamics.

PREREQUISITES
  • Understanding of PWM (Pulse Width Modulation) principles
  • Familiarity with 555 timer IC configurations
  • Basic knowledge of electrical circuits and components
  • Concept of voltage thresholds in capacitor charging and discharging
NEXT STEPS
  • Study the operational principles of the 555 timer IC in astable mode
  • Learn about the effects of varying resistance on PWM duty cycles
  • Investigate the relationship between supply voltage and PWM frequency
  • Explore capacitor charging and discharging dynamics in PWM applications
USEFUL FOR

Electronics enthusiasts, hobbyists working with PWM controllers, and engineers designing circuits with 555 timer ICs will benefit from this discussion.

Steve Collins
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I've carried out some testing on a PWM controller using a 555 timer IC (see attached for circuit diagram) and I am having a little trouble understanding the results.

When the POT resistance is increased the duty cycle decreases. As I understand it, when the resistance is increased the voltage increases (V= IR). So to bring the voltage back down the switch stays closed for longer which means that the duty cycle decreases.


When the POT is left at a constant resistance and the source voltage is increased why does the period decrease and the duty cycle remain constant?

Does this mean that the switching frequency is increasing? If it is, why?
 

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I think you need to read up on how the 555 works. Basically when configured as an oscillator the cap is charged and discharged between 1/3 and 2/3rd of the supply voltage.

The pot has three terminals and (together with the diodes) is set up so that one "side" of the pot is used for the charge phase and the other for the discharge phase. Moving the pot centre tap transfers resistance from the time constant for one phase to the other - so the mark space ratio changes.

Changing the supply voltage alters the "distance" (more correctly the "voltage difference") between 1/3rd VCC and 2/3rd VCC so the frequency will change. For example

At VCC=9V the switching thresholds would be at 3V and 6V a difference of 6-3=3V.

At VCC=10V the switching thresholds would be at 3.33V and 6.66V a difference of 3.33V which is greater. So the capacitor has to charge and discharge "further" before it switches and the frequency will be slightly slower.

Edit: I note that you say the period increases when the source voltage is increased. Is that correct? If so then note that the charging and discharging current also depends on the voltage across the pot which in turn depends on the output voltage swing on pin 3. That also changes with changing VCC. There are a lot of possible interactions. It's been a while since I used a 555 and I forget which dominates.
 
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Thanks for your reply and guidance.

I will look into the 555 with the information you have given me in mind.
 
Last edited:

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