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Searching for software for logic optimization

  1. Aug 4, 2009 #1
    I've got quite an unusual hobby project and so far, after couple of nights googling, I haven't found software that would fit the bill. I've got the truth table representing what I'd like to do and can minimize & map it to gates using Logic Friday.
    The problem is, I don't have NOR or NAND available and Logic Friday won't map to gates without checking one of those as "available". Of course, I can construct those with the gates I have, so Logic Friday gives me a solution. Sadly, that solution is not very optimal because the program thinks that a NOR is just one gate, when in reality, I'd have to use a NOT and a OR.
    Another issue is that I've got some gates(the prime offender being the ANDNOT (p & !q) ) that are not even listed in the menu to select. Therefore, i can't take advantage of those easily and even if i did, the result would probably be less than optimal.
    With the problem size i have, i think i could write something that would brute force every combination of gates from a predefined set and output the one that produces the correct output with the least amount of gates, but i really don't feel like doing that if can avoid it.
     
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  3. Aug 4, 2009 #2

    negitron

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    What exactly are you attempting to do? It's rare these days to require complex assemblies of discreet gates; nearly anything you want can be done with a PIC, PICAxe or BASIC Stamp with just a little programming.
     
  4. Aug 5, 2009 #3
    It's more like... I want to do things the hard way, it doesn't have to be efficient or even practical or anything like that. I still don't want to do unnecessary work, so I need to be economical about my gate usage.
     
  5. Aug 5, 2009 #4

    negitron

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  6. Aug 18, 2009 #5
    Resurrecting this topic after my trip around the Baltic sea...
    The link pretty much talks about how to get the best sum of products representation and how to implement it. That wasn't the problem. Logic Friday already gives the best answer in a few seconds and I could easily implement that. The thing is, I don't know what's the best mapping to the set of gates I can use.
     
  7. Aug 18, 2009 #6
    A long time ago I used a program that might fit then bill. I think it was called espresso and may have been open source and written at UC Berkeley. Haven't seen it in 10 years though.

    Most contemporary design flows, ASIC or FPGA, have a higher level synthesis tool that performs the logic minimization automatically.

    What technology are you using that you can't have a nand gate or a nor gate? In CMOS an AND gate is a NAND gate with an inverter so it doesn't make sense to have an AND gate without a NAND gate. In your design you would have a "AND NOT NOT"( 8 transistors) rather than a NAND (4 transistors).

    If it isn't simple enough to do by hand then why not use a CPLD?
     
  8. Aug 20, 2009 #7
    Actually, I don't have AND gates. What I meant with the sum of products representation is that I can implement it, but I have to use several gates to make an AND. Anyway, I don't like to get into specifics about the project.
    Thanks for the tip about Espresso. Logic Friday is built on it, but maybe there's some code I can reuse. It seems that it's time to give up and do some programming. Oh well, such is life.
     
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