Selecting operation code for arithmetic circuit that uses the least amount of transistors and other inquiry

[mostafaelsan2005]

Homework Statement

I have this truth table i made for an arithmetic circuit with control signals S3 to S0 and C0, I need to pick 3 inputs (three switches SW2 to SW0) that outputs this truth table with a combinational logic circuit using the least amount of transistors possible. How can i go about strategically selecting the inputs so that i can generate a combinational logic circuit that uses the least amount of transistors possible? 0 port of multiplexer is connected to ground for both A and B, 1 is connected to A' or B', 2 and 3 are connected to A or B.

Relevant Equations

All below.

,

I made this truth table, so this would be the output. I need to create a combinational circuit with inputs SW[2:0] that output this with the least amount of transistors. What is the strategy here? I have also attached my planning document:

If you want to know how I selected the control signals (S3 through S0, C0 is fixed based on the operation), it's based on a 4x1 multiplexer where the input for 2 and 3 (10 and 11) are connected to each other to account for the fact that I have three options only for A and B to which both outputs of the multiplexers are connected to a full adder for each bit of vector A and B.

Additionally, I also have some trouble understanding how I will be implementing each full adder. How would I design it so that the full adder adds 1 (when C0 = 1) to the appropriate A or B vector if that makes sense?

 

[Baluncore]

How would I design it so that the full adder adds 1 (when C0 = 1) to the appropriate A or B vector if that makes sense?

Each bit-slice of the full adder has two bits and a carry input, with one bit and carry output. The least significant bit gets input from the carry bit, while the most significant bit generates the new carry.

 

[berkeman]

that output this with the least amount of transistors

You are really asked to implement this at the transistor level and not at the gate level? If so, what kinds of transistors are you allowed to use?

https://tiij.org/issues/issues/spring97/electronics/cmos/cmostran.html

 

[mostafaelsan2005]

You are really asked to implement this at the transistor level and not at the gate level? If so, what kinds of transistors are you allowed to use?

View attachment 358105
https://tiij.org/issues/issues/spring97/electronics/cmos/cmostran.html

No, I am asked to do it at the gate level but still using the least transistors possible. For example, if I am able to reduce the number of gates (including mapping techniques at the end) the number of transistors used will be significantly reduced. Additionally, were taught to use gates with CMOS transistor implementations (so NMOS and PMOS transistors). So like a 2 input AND?OR has 6 transistors, a 2 input NAND/NOR has 4 transistors, a 4 input OR/AND has 10 transistors, etc.

 

[mostafaelsan2005]

Each bit-slice of the full adder has two bits and a carry input, with one bit and carry output. The least significant bit gets input from the carry bit, while the most significant bit generates the new carry.

That makes sense, thank you.