mostafaelsan2005
- 74
- 3
- Homework Statement
- I have this truth table i made for an arithmetic circuit with control signals S3 to S0 and C0, I need to pick 3 inputs (three switches SW2 to SW0) that outputs this truth table with a combinational logic circuit using the least amount of transistors possible. How can i go about strategically selecting the inputs so that i can generate a combinational logic circuit that uses the least amount of transistors possible? 0 port of multiplexer is connected to ground for both A and B, 1 is connected to A' or B', 2 and 3 are connected to A or B.
- Relevant Equations
- All below.
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I made this truth table, so this would be the output. I need to create a combinational circuit with inputs SW[2:0] that output this with the least amount of transistors. What is the strategy here? I have also attached my planning document:
If you want to know how I selected the control signals (S3 through S0, C0 is fixed based on the operation), it's based on a 4x1 multiplexer where the input for 2 and 3 (10 and 11) are connected to each other to account for the fact that I have three options only for A and B to which both outputs of the multiplexers are connected to a full adder for each bit of vector A and B.
Additionally, I also have some trouble understanding how I will be implementing each full adder. How would I design it so that the full adder adds 1 (when C0 = 1) to the appropriate A or B vector if that makes sense?
I made this truth table, so this would be the output. I need to create a combinational circuit with inputs SW[2:0] that output this with the least amount of transistors. What is the strategy here? I have also attached my planning document:
Additionally, I also have some trouble understanding how I will be implementing each full adder. How would I design it so that the full adder adds 1 (when C0 = 1) to the appropriate A or B vector if that makes sense?