likephysics
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Why should the input in any logic be present before the clock?
Is the setup time related to clock rise time?
Is the setup time related to clock rise time?
The discussion revolves around the concept of setup time in digital circuits, particularly its relationship with clock signals and input stability. Participants explore the implications of setup time on circuit performance and the factors influencing it, including clock rise time and internal gate characteristics.
Participants express differing views on the relationship between setup time and clock rise time, with some asserting a connection while others contest this idea. The discussion remains unresolved regarding the exact nature of these relationships.
There are unresolved aspects regarding the assumptions made about internal gate behavior and the specific conditions under which setup time is defined. The discussion also highlights the potential variability in circuit performance based on design choices.
MATLABdude said:Precisely. You want the inputs to be stable before a clock transition in order to ensure that you're reading the right value, and not the previous value, or possibly even worse, some transition value between the two. Why do they say that a value should be stable for X nanoseconds before the clock? Probably because of how things are arranged internally and how they propagate. That or they ran some tests and that was the minimum value that did not result in errors.