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Set-up time in digital circuits

  1. Mar 10, 2009 #1
    Why should the input in any logic be present before the clock?
    Is the setup time related to clock rise time?
  2. jcsd
  3. Mar 11, 2009 #2


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    Precisely. You want the inputs to be stable before a clock transition in order to ensure that you're reading the right value, and not the previous value, or possibly even worse, some transition value between the two. Why do they say that a value should be stable for X nanoseconds before the clock? Probably because of how things are arranged internally and how they propagate. That or they ran some tests and that was the minimum value that did not result in errors.
  4. Mar 11, 2009 #3
    ok. thanks. A year ago, I was trying to use the same signal for clock and data in, it worked in simulator but did not work in the ckt. I had to delay the clock.

    The rise time at the data in and the clock must be different. If they are same, my ckt should have worked.
  5. Mar 11, 2009 #4


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    It's actually not generally related to the clock rise time, because gates are designed to very rapidly change state at a specific trigger voltage. Whether you arrive at that voltage quickly or slowly, the change in state happens with the same quickness.

    The setup time is for charging the capacitance of the transistors inside the gate. Even after maximal voltage has been attained at the gate's input, the transistor gates, junction capacitances, etc. within still must be charged. The amount of time needed to guarantee that the gate reacts properly is called the setup time.

    Quite often, gates can be specifically designed to have zero setup time.

    - Warren
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