Simple Circuits: Understanding Node Voltage Analysis

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Discussion Overview

The discussion revolves around the application of Node Voltage Analysis in circuit analysis, specifically focusing on the use of supernodes when voltage sources are present. Participants explore the conditions under which supernodes should be used, the implications of including or excluding certain components, and the potential confusion arising from different instructional approaches.

Discussion Character

  • Homework-related
  • Technical explanation
  • Debate/contested

Main Points Raised

  • One participant expresses confusion about the use of supernodes in Node Voltage Analysis, noting a discrepancy between their understanding and their teacher's guidance.
  • Another participant clarifies that a supernode includes the reference node and the voltage source but does not include certain resistors, suggesting that the reference node does not require a separate equation.
  • Some participants question when it is appropriate to use supernodes, with one expressing concern about potentially misapplying the concept during exams.
  • A participant mentions that supernodes can vary in size and should encompass nodes whose potentials are fixed by voltage sources.
  • There is a discussion about the necessity of using supernodes when voltage sources connect two nodes, as it complicates the ability to express current in terms of node potentials.
  • One participant acknowledges a mistake in their supernode equation and corrects it based on feedback from others.

Areas of Agreement / Disagreement

Participants generally do not reach a consensus on the best practices for using supernodes, with multiple competing views on when and how to apply them in Node Voltage Analysis. The discussion remains unresolved regarding the optimal approach to supernodes.

Contextual Notes

Participants express uncertainty about the boundaries of supernodes and the implications of including or excluding certain circuit elements. There are also references to specific calculations and equations that are not fully resolved within the discussion.

galaxy_twirl
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Homework Statement



2ptt24l.jpg


Homework Equations



##v1 + v2 + v3 = 0## (KCL)

The Attempt at a Solution



20gjj8w.jpg


I don't understand why my solution is wrong. I was taught that if I were to use Node Voltage analysis, I should put nodes with voltage sources into supernodes which was what I did, however, my teacher showed a rough guide in class and he did not use supernode.

Hence, I am a bit confused now -- when do we use supernodes and if we use supernodes, how big should they be? For the question above, if I were to use supernode, assuming I made some calculation errors above, will I get the same answer as my teacher? Thanks!

My teacher's partial solution:

123qhop.png
 
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A Supernode in this case would include the reference node and the source 2v. It does not include R4. But you don't need to write an equation for the reference node, just the two other nodes, v and v2.
 
gneill said:
A Supernode in this case would include the reference node and the source 2v. It does not include R4.

What do you mean by the reference node? Does it mean that I must not cover the resistor R4?

[/QUOTE]But you don't need to write an equation for the reference node, just the two other nodes, v and v2.[/QUOTE]

I see. Hmm.. Then when we do know when not to use supernode? This is because, I usually would put voltage sources in supernodes whenever I see them in a circuit.. May I know if this is bad practice/a misconception? :(

Thanks! :D
 
First you select a reference node. In this circuit the bottom rail is the natural choice.

Any sources directly connected to the reference node are effectively part of a supernode. But you don't need to write a node equation for the reference node since by definition it has the known potential 0V.

In other locations a supernode comprises a set of nodes whose potentials with respect to each other are fixed by voltage sources and thus independent of any current flowing between them. A resistor in series with a voltage source doesn't work because a change in current changes the potential across the resistor, thus altering the end-to-end potential difference of the combination.
 
I see. OH YA! Sorry about the issue on reference node. I had always called it the "ground -ve 0" node because I always fix it, usually on the negative end of independent voltage sources, and where the end lands on the other nodes with nothing in between the nodes so I can put 0V across left to right and vice versa, so the term reference node slipped my mind. ><

gneill said:
Any sources directly connected to the reference node are effectively part of a supernode. But you don't need to write a node equation for the reference node since by definition it has the known potential 0V.

Ah yes. My teacher said that supernodes can be of any size, since a supernode is a collection of nodes.

gneill said:
In other locations a supernode comprises a set of nodes whose potentials with respect to each other are fixed by voltage sources and thus independent of any current flowing between them. A resistor in series with a voltage source doesn't work because a change in current changes the potential across the resistor, thus altering the end-to-end potential difference of the combination.

I see. So that means I cannot put a supernode at the dependent voltage source, because I will not be able to loop it after and around R4, which makes it look funny, and hence I should not do it. Am I right to say this? I attempted to draw a supernode below, according to what you have said above, to be sure I did not interpret your message wrongly. :)

2gwrkvo.png
 
The reference node and the directly attached sources can be considered a supernode.

Fig1.gif


The potential at the top of v1 is, well, v1. And the potential at the top of the 2v source is 2v. These are fixed potentials with respect to the reference node as set by those sources.
 
gneill said:
The reference node and the directly attached sources can be considered a supernode.

View attachment 75824

The potential at the top of v1 is, well, v1. And the potential at the top of the 2v source is 2v. These are fixed potentials with respect to the reference node as set by those sources.

I see. Thank you for the illustration. :) I shall try solving the question again.

Just wondering, if I were to not use supernodes at all, is it generally okay for Node Voltage Analysis? This is just in case where I get confused in the exam and use supernodes inappropriately. :X (But I will still keep in mind on your advice on how to set the boundaries of supernodes. :D)
 
Hmm.. I still got 3/16 as my answer. :(
 
galaxy_twirl said:
I see. Thank you for the illustration. :) I shall try solving the question again.

Just wondering, if I were to not use supernodes at all, is it generally okay for Node Voltage Analysis? This is just in case where I get confused in the exam and use supernodes inappropriately. :X (But I will still keep in mind on your advice on how to set the boundaries of supernodes. :D)
You'll find that you can't avoid using supernodes if there are voltage sources connecting two nodes (unless you choose an analysis method other than nodal analysis). When two nodes are connected by a voltage source there's no way to write an expression for the current through it in terms of the node potentials and a resistance because there's no resistance value to use.
 
  • #10
galaxy_twirl said:
Hmm.. I still got 3/16 as my answer. :(
Type out your work so we can have a look.
 
  • #11
Here is my working: (I was typing out when you posted this. Haha.)

21mynns.jpg


Thanks! :D
 
  • #12
gneill said:
You'll find that you can't avoid using supernodes if there are voltage sources connecting two nodes (unless you choose an analysis method other than nodal analysis). When two nodes are connected by a voltage source there's no way to write an expression for the current through it in terms of the node potentials and a resistance because there's no resistance value to use.

I see. Thank you for your advice. :D I will keep a lookout for those cases and apply supernodes appropriately.
 
  • #13
Your "supernode" equation is not correct; it has no term for the path through v1 and R1.

But your supernode includes the reference node, so you do not have to write an equation for it. The second node to use is where R3, R4, and R5 come together (that is, v2).
 
  • #14
gneill said:
Your "supernode" equation is not correct; it has no term for the path through v1 and R1.

Oh gosh! @.@ Sorry. I made a careless mistake there. :( I have to add (v-v1)/1 in front of the first equation under SN.

But your supernode includes the reference node, so you do not have to write an equation for it. The second node to use is where R3, R4, and R5 come together (that is, v2).

And hmm.. I shouldn't have written an equation for v cos it overlaps with my equation for the supernode..

I finally got the answer~ Thank you very much! ^^
 

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