# Simple current limiter for LTSpice

1. Sep 18, 2015

### tfr000

Looking for a simple way to limit the current from a voltage source in LTSpice. Not a realistic or practical circuit, just something that will give me the behavior that I want. Hitting a total mental block with this, for some reason.

What I want is for the source to act normally until the connected circuit draws more than X current - at which point it supplies X current and no more. Like a lab power supply.

2. Sep 18, 2015

### shariq92

3. Sep 19, 2015

### tfr000

Not exactly, but that does give me an idea or two. I don't know why information on this seemingly simple and common circuit is so difficult to find.

4. Sep 19, 2015

### meBigGuy

I am not an LTSpice user, so my help is only high level. I don't know of a simple way to do it.

1. Use a voltage dependent voltage source as the main source.
2. Monitor the current with a current dependent voltage source.
3. Reduce the source voltage (in 1 above) when the current sensed by 2 goes above a certain level. (requires a control amplifier with a reference reference and some sort of output clamping)
(note than an opamp is basically a voltage dependent voltage source with high gain)
Perhaps an Arbitrary behavioral voltage source could provide clamping in the control amp.

http://ltwiki.org/?title=B_sources_(complete_reference)

There is probably some neat trick to do this, but I don't know it. Spice has a table driven source that can supposedly do it, but I don't see it in LTSpice

Last edited: Sep 19, 2015
5. Sep 21, 2015

### Staff: Mentor

6. Sep 21, 2015

### meBigGuy

Good simple circuit.
Seems like there should be a cool way to build a simple version of that with ideal sources. Q1 as a VDVS and R/ Q2 as a CDVS.

7. Sep 23, 2015

### tfr000

Ok, so here's what I dreamed up...
In the first, a current-controlled voltage source (an "H" source) is tied to a typical small-resistance current sensor. This one can be adjusted in various ways by messing around with the various parameters, for instance, to get a "soft" current limit.

In the second, you get a hard current limit from an ideal current source, and a hard voltage limit from an ideal zener

8. Feb 13, 2016

### Pasqo

The trick is very simple and effective, adding an ideal diode to any voltage source with the Ilimit parameter set (along with Ron=0 for perfect ideal behavior) will limit the current sourced to the specified value.
To also limit the current sink add another diode in parallel but reversed.
The diode model takes care of smoothing the discontinuity when switching between regions so that the simulation converges properly.

9. Feb 16, 2016

### Pasqo

I have added a symbol and corresponding sub-circuit so that the current limiter device ilim can be selected from the components list and configured through the right click menu.

Rename file ilim_asy.txt to ilim.asy and ilim_cir.txt to ilim.cir and drop in the directory where you store your local components (or the LTspice library dir) and make sure that directory can be selected from within the component window.
After adding the component, in the right click configuration pane along with the current limit, optional series resistance and fixed voltage drop can be also specified (just added some random V and R numbers here, R and V are zero for the plot showed below).

I use these for instance to model AVR microntroller pins which are current limited at 40mA and with approximately 30Ω of (MOSFET) Ron.
The plot below shows the current limit in both directions in explicit action ...

#### Attached Files:

File size:
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• ###### ilim_cir.txt
File size:
381 bytes
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10. Jun 1, 2016

### jpm

Pasqo, that worked great for me. Thank you Sir!

11. Jun 2, 2016

### the_emi_guy

The way to do this in LTSpice is with an "arbitrary behavioral voltage source" (type in "behavioral" in LTSpice help/search).

This save you from having to design an actual circuit that creates this behavior (which may not be ideal). Instead, simply describe the behavior you want mathematically.

http://www.linear.com/solutions/6106

12. Jun 2, 2016

### jpm

the_emi_guy,

how do you do it then? i was playing around with bi and bv sources, but don't see any options to limit current.

Unless you know of some trick with one of ltspice's math functions, i think Pasqo's solution is quite elegant and the best.

Regards

13. Jun 8, 2016

### Erik Haverkamp

Thanks Pasqo!!!!

14. Jun 8, 2016

### the_emi_guy

Agreed! Great solution. My initial impression was that this could be done with bi, bv but I think I was wrong.

15. Aug 1, 2016

### timuryigit

How do I actually use this component?

I've just connected a capacitor to it and added the GND port.
However, all simulations show a flat line when I plot them.

Cheers Timur

16. Aug 2, 2016

### Baluncore

Welcome to PF.
Attach to a post your circuit.asc but add a .txt suffix to make circuit.asc.txt
We can then run your design and work out what is missing.

17. Aug 2, 2016

### timuryigit

cheers Timur

#### Attached Files:

• ###### super_cap_charge_current_source_ilimit_asc.txt
File size:
554 bytes
Views:
151
18. Aug 2, 2016

### timuryigit

Sorry guys beginner mistake the post from pasko from the Feb 17, 2016.
Has actually a circuit which I didn't not pay attention to. Anyway in the circuit I uploaded I did not have V source. Because I thought this is done by the Imilit source

19. Jan 2, 2017

### SpiceGirls

Hi,
I have developed a one-line current limited voltage source. It works in the NI Multisim SPICE environment which uses the SPICE 3:
Bx 1 2 V= { G * V(3, 4) * (Abs(I(Bx)) < Imax ? 1 : 1 - (Abs(I(Bx))/Imax - 1)/k) }
where

• Bx the name of the new B-type component
• 1, 2 the output pins
• 3, 4 the input pins (it controls the voltage between 1 and 2)
• G is the gain from V(3, 4) to V(1, 2)
• Imax is the maximal output current (in Ampere)
• k is a <1 factor which controls the degradation speed of output voltage over the Imax limit (e.g. k=0.2 means that between Imax and 1.2 * Imax the output voltage will linearly goes to zero)

I hope it will be useful for you.

20. Jan 2, 2017

### SpiceGirls

I present you a Multsim simulation result of running a test circuit for the component above (the input and output signals are shifted down and up):