Engineering Solve RC Circuits Homework: Find Vout w/S1+S2 Closed

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The discussion focuses on solving an RC circuit homework problem involving two switches, S1 and S2, with S1 always closed and S2 closed until the capacitor voltage reaches 2V. The participant has derived the voltage across the capacitor, Vc(t), but is confused about applying Kirchhoff's Voltage Law (KVL) to the circuit while the capacitor is charging. Clarifications reveal that V0 is the initial voltage of the capacitor, which is not zero, and V1 is the source voltage. The analysis emphasizes that voltage division among resistors is valid only when the current through them is the same, which occurs only after the capacitor is fully charged. The discussion concludes with the need for clearer problem definitions to avoid confusion.
erezb84
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Homework Statement


S1 switch - always close.
S2 switch is closed, until the capacitor voltage reaches 2V.
given: R,C,V values.
V0 = 0V.
Need to find Vout while S1+S2 are closed and until S2 opens.

Homework Equations


Vc(t) = (Vi - Vf)*(exp -t/TAU) + Vf

The Attempt at a Solution


I have found the Vc(t) equation (until S2 opens) and got:
Vc(t) = 2/3V1*(1-exp(-3t/5RC))
but now i am alittle bit confused.
can't i tell that by KVL for the large loop (throught S2) each R has V1/3 voltage?
or i can't do it because we are in the charging stage?
thanks.
 

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If S1 is always closed, why show it? It's just a wire ...
 
because in the next question it opens...
 
Oh, OK.

Where is V0 and what is V1?
 
V0 is the capacitor initial voltage.
V1 is the source voltage
 
Vout = V1(1/2.5 - 1/3)exp(-t/T) + V1/3

T = {R + R||2R}C.

Initially you have C charged to V1 so the Thevenin equivalent is V1 connected to the rest of the circuit by R/2. So Vout(0+) = V1R/(2.5R). At t = ∞ you have C out of the picture so Vout(∞) = V1/3.

You know the output must take the form Vout = a*exp(-t/T) + b. So you fit a and b:
Vout()+) = a + b, V(∞) = b.

Then T is by inspection R + R||2R since that is the total impedance C sees going to hard voltages (impedance = 0).
 
erezb84 said:
V0 is the capacitor initial voltage.
V1 is the source voltage

If V0 is initial capacitor voltage, it is not zero. It is V1.

I assume V1 is constant, -∞ < t < +∞
S1 closed.
S2 open, t < 0 and closed, t > 0.

If this is incorrect you need to define the problem better.

See you in about 8 hrs.
 
erezb84 said:
can't i tell that by KVL for the large loop (throught S2) each R has V1/3 voltage?
Series resistors [any number of] can be considered to form a simple proportional voltage divider ONLY if all carry the same current. Clearly, that is true in your case ONLY if zero current is going into the capacitor branch. This condition (of zero capacitor current) becomes true only once the capacitor has reached full charge. So that potential divider sets the voltage the capacitor eventually could attain, but until then, one of the resistors carries more current than do the other two.
 
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