Threshold voltage shift vs temperature

Click For Summary
SUMMARY

The discussion centers on the relationship between threshold voltage and temperature in field effect transistors (FETs), specifically silicon-based devices. It is established that the threshold voltage decreases with increasing temperature due to the narrowing of the bandgap, despite the mobility degradation caused by phonon scattering. The conductivity in doped semiconductors is primarily influenced by carrier mobility rather than the number of thermally generated carriers, which remain negligible compared to the fixed number of dopant carriers. Consequently, the frequency of ring oscillators decreases with temperature, contradicting initial assumptions about increased conductivity leading to higher frequencies.

PREREQUISITES
  • Understanding of field effect transistors (FETs)
  • Knowledge of semiconductor physics, particularly bandgap and carrier mobility
  • Familiarity with the effects of temperature on electronic device performance
  • Basic principles of ring oscillator design and operation
NEXT STEPS
  • Research the impact of temperature on silicon bandgap and threshold voltage
  • Explore the relationship between phonon scattering and carrier mobility in semiconductors
  • Investigate the performance characteristics of wide bandgap semiconductors like SiC at high temperatures
  • Study the design and optimization of ring oscillators for varying temperature conditions
USEFUL FOR

Electrical engineers, semiconductor physicists, and anyone involved in the design and optimization of electronic devices operating under varying thermal conditions.

ZeroFunGame
Messages
93
Reaction score
5
TL;DR
In a field effect transistor, does the threshold voltage decrease with increasing temperature? Imagine that there would be an increase in thermally generated carriers and thus the device would reach saturation faster? I realize the mobility would decrease, but the increase of thermal carriers outpaces phonon scattering effects such that conductivity rises. Is this the correct way to think about threshold voltage as a function of temperature?
In a field effect transistor, does the threshold voltage decrease with increasing temperature? Imagine that there would be an increase in thermally generated carriers and thus the device would reach saturation faster? I realize the mobility would decrease, but the increase of thermal carriers outpaces phonon scattering effects such that conductivity rises. Is this the correct way to think about threshold voltage as a function of temperature?
 
Engineering news on Phys.org
-2 mV/K for silicon
 
Is it because the conductivity increases? If the threshold voltage does decrease, wouldn't this make a ring ossilator have an increasing fmax as T increased?
 
ZeroFunGame said:
Is it because the conductivity increases? If the threshold voltage does decrease, wouldn't this make a ring ossilator have an increasing fmax as T increased?
No. Conductivity decrease with increased temperature is a separate effect from narrowing of bandgap which results in threshold voltage shift. And regarding current, mobility degradation typically dominates over threshold voltage shift unless transistor biased in very narrow range of gate voltages near threshold voltage. Therefore, the ring oscillator frequency falls with temperature.
 
trurle said:
No. Conductivity decrease with increased temperature is a separate effect from narrowing of bandgap which results in threshold voltage shift. And regarding current, mobility degradation typically dominates over threshold voltage shift unless transistor biased in very narrow range of gate voltages near threshold voltage. Therefore, the ring oscillator frequency falls with temperature.

As I understand it, conductivity increases with temp in a semiconductor rather than decrease.
Fig 2.2.39 here: https://archive.cnx.org/contents/64...y-in-semiconductor-metal-and-its-conductivity

So the reason for the decrease in threshold voltage is due to a decreasing bandgap.

So you are saying mobility degradation due to phonon scattering is the main reason for reduced oscillator frequency with temperature? Even if conductivity increases?
 
ZeroFunGame said:
As I understand it, conductivity increases with temp in a semiconductor rather than decrease.
Fig 2.2.39 here: https://archive.cnx.org/contents/64...y-in-semiconductor-metal-and-its-conductivity
You are mixing here the behavior of intrinsic conduction in high-purity semiconductor (actually intrinsic conduction was experimentally observed for germanium, but required materials purity is too good for modern silicon technology) and behavior of actual electronic devices which nearly never use intrinsic conduction, instead relying on fully ionized doping to provide charge carriers. Devices based on doped semiconductor have approximately fixed number of carriers and carriers mobility roughly proportional to T^(-2.5).
ZeroFunGame said:
So you are saying mobility degradation due to phonon scattering is the main reason for reduced oscillator frequency with temperature? Even if conductivity increases?
It is a bit meaningless statement. Small-signal conductivity have a direct relation to carriers mobility.
 
Last edited:
So as T increases, the thermally generated carriers do not help with conduction in a doped semiconductor device? But only in the intrinsic semiconductor case?
 
  • Like
Likes trurle
Why are thermally generated carriers negligible in a doped semiconductor? Is it because the dopant density >> thermally generated intrinsic carrier density? Is this still true for wide bandgap semiconductors that have shown IC operation in >500C (for example SiC)? That is, the thermally generated carriers do not help much in a 500C environment?
 
ZeroFunGame said:
Is it because the dopant density >> thermally generated intrinsic carrier density? Is this still true for wide bandgap semiconductors that have shown IC operation in >500C (for example SiC)?
True. Especially for wide bandgap semiconductors. Wider bandgap, less thermal carriers. The limiting factor for SiC at high temperature is actually failure due migration of dopants, not because of proliferation of thermal charge carriers.

Overall, i do not see where "thermally generated carriers" may be helpful. They may increase on current, but also increase off current by same amount. Pure waste of power except for may be non-existing exotics like "reversible anti-fuse".
 
  • #10
trurle said:
True. Especially for wide bandgap semiconductors. Wider bandgap, less thermal carriers. The limiting factor for SiC at high temperature is actually failure due migration of dopants, not because of proliferation of thermal charge carriers.

Overall, i do not see where "thermally generated carriers" may be helpful. They may increase on current, but also increase off current by same amount. Pure waste of power except for may be non-existing exotics like "reversible anti-fuse".

Figure 5 in the link below shows the correlation of conductivity on T for *extrinsic* semiconductor:
https://nptel.ac.in/content/storage2/courses/113106062/Lec8.pdf

This is what I had in mind, where as T increases the conductivity also increases. However, you mentioned that due to dopants >> intrinsic carriers, the conductivity is not dominated by the number of carriers, but by mobility. If mobility continues to degrade due to phonon scattering with increasing T, why is it that conductivity increase at high T for an extrinsic semiconductor?
 
  • #11
ZeroFunGame said:
Figure 5 in the link below shows the correlation of conductivity on T for *extrinsic* semiconductor:
https://nptel.ac.in/content/storage2/courses/113106062/Lec8.pdf

This is what I had in mind, where as T increases the conductivity also increases. However, you mentioned that due to dopants >> intrinsic carriers, the conductivity is not dominated by the number of carriers, but by mobility. If mobility continues to degrade due to phonon scattering with increasing T, why is it that conductivity increase at high T for an extrinsic semiconductor?
Figure 2,3, and 5 in your reference have conductivity increase at high temperature due incomplete ionization of (arbitrary) dopant. Practical devices select dopant of "shallow" type, which ionize completely below 200K. Such dopant selection (boron, phosphorus, arsenic in silicon) allows better stability of device parameters over extended temperature range.
 
  • #12
trurle said:
Figure 2,3, and 5 in your reference have conductivity increase at high temperature due incomplete ionization of (arbitrary) dopant. Practical devices select dopant of "shallow" type, which ionize completely below 200K. Such dopant selection (boron, phosphorus, arsenic in silicon) allows better stability of device parameters over extended temperature range.

I see, so the plot represent deep donor levels. Basically, you are saying that at high enough T, if Figure 5 continued to extend to the left, then the mobility would peak (representing the complete ionization of all donors) and eventually begin to reduce due to phonon scattering?
 
  • Like
Likes trurle
  • #13
ZeroFunGame said:
I see, so the plot represent deep donor levels. Basically, you are saying that at high enough T, if Figure 5 continued to extend to the left, then the mobility would peak (representing the complete ionization of all donors) and eventually begin to reduce due to phonon scattering?
The correct statement would be
"at high enough T, if Figure 5 continued to extend to the left, then the conductivity would peak (representing the complete ionization of all donors) and eventually begin to reduce due to phonon scattering".
conductivity~number_of_carriers*mobility_of_carriers
 
  • #14
trurle said:
The correct statement would be
"at high enough T, if Figure 5 continued to extend to the left, then the conductivity would peak (representing the complete ionization of all donors) and eventually begin to reduce due to phonon scattering".
conductivity~number_of_carriers*mobility_of_carriers

In reference to Fig 5 here: https://www.semanticscholar.org/pap...-Hou/058f3e4087df56522a8b98d84a67f2effa598cda

It looks to me like f_osc increase with T from RT to 300C - 400C (depending on supply voltage), before decreasing. Similarly, the inverter delay is reduced at higher T up until 400C.

This is counter intuitive to what I would expect from transistor performance from RT to 400C, since wouldn't increase in lattice scattering add to the delay and thus reduce the RO frequency as T increased?
 
  • Like
Likes trurle
  • #15
ZeroFunGame said:
In reference to Fig 5 here: https://www.semanticscholar.org/paper/A-600-°C-TTL-Based-11-Stage-Ring-Oscillator-in-Shakir-Hou/058f3e4087df56522a8b98d84a67f2effa598cda

It looks to me like f_osc increase with T from RT to 300C - 400C (depending on supply voltage), before decreasing. Similarly, the inverter delay is reduced at higher T up until 400C.

This is counter intuitive to what I would expect from transistor performance from RT to 400C, since wouldn't increase in lattice scattering add to the delay and thus reduce the RO frequency as T increased?
From abstract, seems the device is highly anomalous. Unfortunately, cannot say why because the full text is behind paywall.
 
  • #16
trurle said:
From abstract, seems the device is highly anomalous. Unfortunately, cannot say why because the full text is behind paywall.

TTL implies BJT, so I was wondering if they behaved differently than majority carrier devices like JFETs or MOSFETs. My initial thought was that at higher T, the natural depletion region is reduced, so this could imply faster switching operation, but was just a guess and not entirely sure if the logic follows.
 
  • #17
ZeroFunGame said:
TTL implies BJT, so I was wondering if they behaved differently than majority carrier devices like JFETs or MOSFETs. My initial thought was that at higher T, the natural depletion region is reduced, so this could imply faster switching operation, but was just a guess and not entirely sure if the logic follows.
Base width modulation in other words may be. Without full-text it remain a unproven hypothesis though. I requested a full text at researchgate.net, let`s wait for the author response.

P.S. From figures seems the anomaly is due low-doped resistors at collector which seems to be going into intrinsic conduction mode at high temperature. The logic high is 5V below supply rail at room temperature - likely indicating the collector resistors value were higher than optimal for best speed.
 
Last edited:

Similar threads

  • · Replies 9 ·
Replies
9
Views
498
  • · Replies 3 ·
Replies
3
Views
4K
  • · Replies 1 ·
Replies
1
Views
5K
  • · Replies 2 ·
Replies
2
Views
2K
  • · Replies 4 ·
Replies
4
Views
10K
  • · Replies 17 ·
Replies
17
Views
2K
  • · Replies 19 ·
Replies
19
Views
2K
  • · Replies 9 ·
Replies
9
Views
3K
  • · Replies 35 ·
2
Replies
35
Views
5K
Replies
9
Views
4K