Time Delay Chart: Understanding Circuit Diagram and Output Hazards

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Discussion Overview

The discussion revolves around understanding a time delay chart related to a circuit diagram, specifically focusing on the propagation delays and output hazards associated with the logic circuit. Participants are seeking clarification on how to accurately represent the timing and behavior of the circuit outputs based on input changes.

Discussion Character

  • Exploratory
  • Technical explanation
  • Debate/contested
  • Homework-related

Main Points Raised

  • One participant asks for help in drawing a time chart based on a friend's circuit diagram, noting that inputs A, B, and C emit a hazard at output Y.
  • Another participant describes the sequence of events, stating that A starts as a pulse, B transitions from 1 to 0 at time t0, and B' becomes 1 at time t1 after passing through an inverter, leading to AB' becoming 1 at time t2 after an AND gate delay.
  • A participant requests further clarification on the behavior of output Y and the state of B after t0, indicating a need for more detailed explanation.
  • One participant mentions tracing propagation delays to determine how long it takes for input changes to affect output Y, questioning the actual problem statement related to the circuit.
  • Another participant seeks to clarify how to determine the duration of the propagation delays and asks which input(s) are relevant for finding the time until Y is stable.

Areas of Agreement / Disagreement

Participants express uncertainty regarding the timing and propagation delays in the circuit, with no consensus on the specific problem statement or how to calculate the time delays involved.

Contextual Notes

Limitations include unclear definitions of the problem statement and the specific propagation delay times (tpd) required for the circuit analysis. The discussion does not resolve how to determine the stability of output Y based on input changes.

Who May Find This Useful

Individuals interested in circuit design, timing analysis, and logic circuit behavior may find this discussion relevant.

MissP.25_5
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Hello, can someone please tell me how to draw this time chart? I got this from a friend and I don't understand how he got it.
A, B, C emit hazard at output Y.

Here are the circuit diagram and the time delay my friend drew.
 

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looks like A starts out as 1 pulse

B goes from 1 to o at t0

B' goes thru the inverter and becomes a 1 at t1 (it takes time for the NOT gate to output the new state)

consequently AB' becomes a 1 at t2 (it takes time for the AND gate to output the new state)

Does that make sense?
 
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jedishrfu said:
looks like A starts out as 1 pulse

B goes from 1 to o at t0

B' goes thru the inverter and becomes a 1 at t1 (it takes time for the NOT gate to output the new state)

consequently AB' becomes a 1 at t2 (it takes time for the AND gate to output the new state)

Does that make sense?

what about Y and what about B after t0? Could you explain those too so I can see how it goes? Please...
 
He/she is just tracing the propagation delays through the logic to figure out how long it takes for changes at the inputs to propagate to the output Y.

What is the actual problem statement? The circuit looks related to your other thread, BTW?
 
berkeman said:
He/she is just tracing the propagation delays through the logic to figure out how long it takes for changes at the inputs to propagate to the output Y.

What is the actual problem statement? The circuit looks related to your other thread, BTW?

My problem is how to know how long it takes.
 
MissP.25_5 said:
My problem is how to know how long it takes.

How long what takes? Do you need to find how many prop delay times (tpd) it takes from one of the inputs changing until Y is stable? Which input(s)?
 

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