Time Delay Chart: Understanding Circuit Diagram and Output Hazards

[MissP.25_5]

Hello, can someone please tell me how to draw this time chart? I got this from a friend and I don't understand how he got it.
A, B, C emit hazard at output Y.

Here are the circuit diagram and the time delay my friend drew.

 

[jedishrfu]

looks like A starts out as 1 pulse

B goes from 1 to o at t0

B' goes thru the inverter and becomes a 1 at t1 (it takes time for the NOT gate to output the new state)

consequently AB' becomes a 1 at t2 (it takes time for the AND gate to output the new state)

Does that make sense?

 

[MissP.25_5]

looks like A starts out as 1 pulse

B goes from 1 to o at t0

B' goes thru the inverter and becomes a 1 at t1 (it takes time for the NOT gate to output the new state)

consequently AB' becomes a 1 at t2 (it takes time for the AND gate to output the new state)

Does that make sense?

what about Y and what about B after t0? Could you explain those too so I can see how it goes? Please...

 

[berkeman]

He/she is just tracing the propagation delays through the logic to figure out how long it takes for changes at the inputs to propagate to the output Y.

What is the actual problem statement? The circuit looks related to your other thread, BTW?

 

[MissP.25_5]

He/she is just tracing the propagation delays through the logic to figure out how long it takes for changes at the inputs to propagate to the output Y.

What is the actual problem statement? The circuit looks related to your other thread, BTW?

My problem is how to know how long it takes.

 

[berkeman]

My problem is how to know how long it takes.

How long what takes? Do you need to find how many prop delay times (tpd) it takes from one of the inputs changing until Y is stable? Which input(s)?