Engineering Why Does the Output Y Differ in the Moore Circuit Timing Diagram?

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The discussion centers on understanding the output behavior of a Moore type sequential circuit with a D flip-flop and a combinational circuit. Participants are confused about why the output Y is 1 during the 5th clock cycle despite calculations suggesting it should be 0. The key point emphasized is that the circuit's sequential nature means the output depends on the inputs present at the AND gate during each clock pulse, rather than solely on the current values of X or its complements. Clarifications are made regarding the importance of timing diagrams in representing the circuit's reality, and the need to complete an incomplete state transition diagram based on specific input sequences. The conversation highlights the distinction between theoretical calculations and practical circuit behavior.
  • #31
So then look for resources that address the foundations and fundamentals of both analysis and synthesis. These are the books I have used:

The Art of Digital Design (Winkel, Prosser)
Digital Circuits and Microprocessors (Taub)

They are relatively affordable (used, from Amazon).

I'm sure there are plenty of on-line resources as well.
 
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  • #32
fiksx said:
thanks for the help! :D
Sure...
 

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