This is just an example/solution to a timing diagram/gate delay for the circuit of logic gates. I am reading ahead of the chapter on gate delays & time diagrams, however, the book doesn't provide as much information. I am unsure how the solution came about in drawing their timing diagram from scratch, and thought maybe someone could help clarify this to me? Are they simply taking consideration of the time delays FIRST or the initial states FIRST?
The Attempt at a Solution
I understand that when the input to a logic gate is being changed, its output won't change instantaneously. Also that switching elements within the gate take some amount of time to react to a change in input, so that the change in the gate output is delayed with respect to input change.