# Need clarification on Gate Delays & Diagrams

• Aristotle
In summary: I understand. The orange line is there to show that the output of the gate changes 5ns after the input changes, but before the output is actually applied. Thanks for clearing that up for me.In summary, the solution to drawing a timing diagram for a logic gate involves taking into account the time delays for the gate's inputs and outputs.
Aristotle

## Homework Statement

This is just an example/solution to a timing diagram/gate delay for the circuit of logic gates. I am reading ahead of the chapter on gate delays & time diagrams, however, the book doesn't provide as much information. I am unsure how the solution came about in drawing their timing diagram from scratch, and thought maybe someone could help clarify this to me? Are they simply taking consideration of the time delays FIRST or the initial states FIRST?

.

n/a

## The Attempt at a Solution

I understand that when the input to a logic gate is being changed, its output won't change instantaneously. Also that switching elements within the gate take some amount of time to react to a change in input, so that the change in the gate output is delayed with respect to input change.

I'm not sure what you don't understand. The initial states and timing of X are given, and you are supposed to draw the states of Y and Z as a consequence of the change in state of X. For example:
(1) X changes at 10ns
(2) 10ns later (at 20ns) Z changes
(3) 5ns later (at 25 ns) Y changes
(4) 10ns later (at 35 ns) Z changes
etc...

berkeman
Hello Phyzguy,

Yes, I understand the set up for the initial states. Here is what I have so far:

Initially X=0, Y= 1, and the output became 0. So as '0'--the output, makes its way to the inverter, there is a 5ns delay (which I denoted in ORANGE) before actually "inverting" from '0' to '1'. As X and Y makes its way to the and gate, there is also a 10ns which I also denoted in orange. Am I on the right track?

Also in the graph that I've drawn...is it correct or not that I draw a '1' of only length 5ns in the 'Z' row (from 20ns to 25ns) , or must it extend from 20-30ns? That is the part I am confused with, and as continuing with the completion of the graph. Any advice would be appreciated. Thanks!

I don't understand why you have the orange line from 10-15 ns in Y. You should assume at the beginning that the signals X,Y,Z have been in their states for a long time and nothing is changing. Then at 10ns, X changes from 0 to 1. This will not cause any immediate change to Y, since Y is not dependent on X, so why do you have an orange line in Y? ? However, after 10ns, the change in X will lead to a change in Z (the orange line and the change in Z at 20ns look correct). If nothing else changes, Z will stay that way forever, not just for 5 ns. However, the change in Z causes a change in Y 5 ns later, and that change in Y causes a change in Z 10 ns later. Does that help?

phyzguy said:
I don't understand why you have the orange line from 10-15 ns in Y. You should assume at the beginning that the signals X,Y,Z have been in their states for a long time and nothing is changing.
My thought process at first was that initially when X=0 and Y=1, then Z= 0...after '0' makes its way to the inverter, then you would take consider of the 5ns delay.

phyzguy said:
You should assume at the beginning that the signals X,Y,Z have been in their states for a long time and nothing is changing.
So you're saying that Y should not have a 5ns delay immediately, but until 'Z' changes? I know that X's inputs will determine the change in Z. Sorry I am a little slow trying to visualize the concept. Would it be possible for you to pinpoint what you're trying to say with the graphing diagram solution in the example?

phyzguy said:
Then at 10ns, X changes from 0 to 1.
Yes I understand that part.

phyzguy said:
I don't understand why you have the orange line from 10-15 ns in Y. You should assume at the beginning that the signals X,Y,Z have been in their states for a long time and nothing is changing. Then at 10ns, X changes from 0 to 1. This will not cause any immediate change to Y, since Y is not dependent on X, so why do you have an orange line in Y? ? However, after 10ns, the change in X will lead to a change in Z (the orange line and the change in Z at 20ns look correct). If nothing else changes, Z will stay that way forever, not just for 5 ns. However, the change in Z causes a change in Y 5 ns later, and that change in Y causes a change in Z 10 ns later. Does that help?

Okay I thought about what you said..but I still have a question..
If I understand you correctly, as x changes from either 0 to 1 or 1 to 0, then a 10 ns delay is considered for Z. As for when Z changes from 0 to 1, or 1 to 0, then a 5ns is considered for Y.

So INITIALLY, I see that X=0, Y=1, and Z= 0.
Then I see that X changes from 0 to 1. Okay so that means we will consider a 10ns delay for Z. Y remains unchanged.

Next, when Z's output becomes 1, Z changes, so then there will BE a 5ns DELAY, correct so far?...X remains unchanged--still '1'. so we DONT take consider of a 10ns delay.

My question is about drawing the graphs...

which one is appropriate, the first or second? I am confused on whether drawing only a '5ns line' on row Z or a '10 ns line'.

Aristotle said:
My question is about drawing the graphs...
which one is appropriate, the first or second? I am confused on whether drawing only a '5ns line' on row Z or a '10 ns line'.

Well, neither one is correct. You should draw a 15ns line for Z. After Z transitions high, it will stay high until 10ns after one of the inputs to the AND gate changes again. X will not change until much later, so when will Y change? Y will change 5ns after Z changes. So Z will stay high for 15 ns. I think what you are missing is that, while it takes 10ns for a change to propagate through the AND gate, after the output has changed, the output will retain its state indefinitely until one of the inputs changes again. It doesn't just go high for 10 ns and then go back where it was.

What phyzguy said. I prefer to draw arrows on the drawing to show the delays..

## 1. What are gate delays and why are they important?

Gate delays refer to the amount of time it takes for a digital logic gate to change its output in response to a change in its input. They are important because they affect the overall speed and performance of a digital circuit.

## 2. How do gate delays affect the timing of a circuit?

Gate delays can cause a delay in the propagation of signals through a circuit, which can impact the overall timing of the circuit. If there are multiple gates in a circuit, the cumulative delay of each gate can add up, causing a longer overall delay.

## 3. What factors can affect gate delays?

There are several factors that can affect gate delays, including the type of logic gate used, the materials and technology used in the fabrication of the gate, and the temperature and voltage levels at which the gate is operating.

## 4. How are gate delays represented in circuit diagrams?

Gate delays are typically represented by a small symbol or notation next to the logic gate in a circuit diagram. This symbol can vary depending on the specific type of gate delay being represented, such as input-to-output delay or output transition delay.

## 5. How can gate delays be minimized?

There are a few ways to minimize gate delays, such as using faster logic gates, optimizing the circuit layout and design, and using techniques like pipelining and parallel processing. Additionally, choosing the appropriate voltage and temperature levels for a circuit can also help reduce gate delays.

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