Time domain aliasing in VNA TDR measurement

[yefj]

Hello, alyasing by nyquist theorem where we have analog signal at some frequency and we sample it at some rate so we need the sample rate to be twice higher the the analog signal frequency.

we set TDR in VNA from negative to positive -50ns to 50ns for example
we have a circular 100s.
Our signal traveling forward then reflected signal sums with the original after a while.
this time for the reflected signal to reach the source is 2*length_till_discontinuety/phase velocity.
We start time at t=0sec
How does Aliasing comes at this point?
How Do we set the VNA time domain properly so we avoid time domain Aliasing?

 

[yefj]

Update:
so given velocity factor 77% and cable length of 0.3m given the calculation in the photo we have round trip at 2.3ns.
so given my calculation is from -50ns to 50ns I will have the TDR pulse only on the positive side.

The problem with this consept is if we have a system where we have back and forth reflections where source and load impedance differ the carateristic impedance of the line.
Then we have bounce diagram from 0 to infinity .

but in VNA we wont have time infinity we have circular time .
How double mismatch source and load will be presented on circular VNA plot?
Thanks.

 

[Baluncore]

The problem with this consept is if we have a system where we have back and forth reflections where source and load impedance differ the carateristic impedance of the line.
Then we have bounce diagram from 0 to infinity .

Each "bounce" is a scattering event that splits the energy two ways, in proportion to the transmission and reflection coefficient at each impedance transition. The signal will be attenuated progressively, so multiple scatterings quickly become an insignificant part of the record.
Transmission lines also have attenuation with distance travelled, which means as time increases signals in TDR become less well-defined.

The process of computing a TDR from VNA data, needs to be separated into discrete and separate steps before analysis.

Maybe you should start by looking at how a VNA operates.
https://en.wikipedia.org/wiki/Network_analyzer_(electrical)#Architecture

 

[yefj]

Hello Baluncore, suppose in VNA we have -50ns to 50ns.
I understand that if we have signal in 0 to -50ns negative area is called casuality.
That things happen before the input.
If I understand correcly it could happen because of bad deembeding or bad sampling of the S-params, or bad rise time
Few questions:
1.does signal appearing in the negative area -50ns to 0 means causality issue?
2.why bad deembeding causes reflection in negative area?
3.why bad sampling of s-params can cause its IFFT to have signal in the negative area?
4.How can I know the cause of bad causality issue?
5.what is the proper way to sample S-params so I will not have causality problem?
Thanks.