Understanding 10GHZ CPU Technology: Obstacles and Resources

[MathematicalPhysicist]

What are the current obstacles from having one core 10 GHZ CPU processor?

What books/courses do you propose to read/take in order to understand the theory behind CPU technology?

I assume how to cool such a processor is one of the obstacles, but there are more, right?

 

[cpscdave]

A couple things come to mind here.
First as you mentioned cooling is an issue.
I'm not sure they have any crystal they could use to build an oscillator that fast (not sure about that though)
Other components slow down the computer too much, HD, Memory access so there may not even be an advantage to go that fast.
Signal propagation delays become even more of an issue. In the current processor pipeline there are wasted cycles to simply allow the signal to travel far enough.

Cost is probably a large driving factor as well. We hit a point where it was more cost effective to improve performance with other methods (cleaner ISA, caching, better compiler optimizer)

 

[Mech_Engineer]

Most of the reason comes down to current design conventions reaching the limits of what transistors are capable of. There's a useful blog post on the topic here: https://www.comsol.com/blogs/havent-cpu-clock-speeds-increased-last-years/.

...The scaling of voltage and current with length is reaching its limits, since transistor gates have become too thin, affecting their structural integrity, and currents are starting to leak.

Furthermore, thermal losses occur when you are putting several billions of transistors together on a small area and switching them on and off again several billion times per second. The faster we switch the transistors on and off, the more heat will be generated. Without proper cooling, they might fail and be destroyed. One implication of this is that a lower operating clock speed will generate less heat and ensure the longevity of the processor. Another severe drawback is that an increase in clock speed implies a voltage increase and there is a cubic dependency between this and the power consumption...

...The overwhelming benefit of multicores can be derived from the following reasoning: When cutting down the clock speed by 30%, the power is reduced to 35% of its original consumption, due the cubic dependency (0.7*0.7*0.7 ~ 0.35).

Yet, computing performance is also reduced by 30%. But when operating two compute cores running with 70% of the original clock speed, we have 140% of the original compute power using only 70% of the original power consumption (2 x 35%).

 

[meBigGuy]

I'm not sure they have any crystal they could use to build an oscillator that fast (not sure about that though)

Check out Gallium Arsenide

As for cmos and liquid nitrogen or helium cooling:
http://www.neowin.net/news/amd-vishera-cpu-sets-a-world-record-867ghz-frequency
http://www.anandtech.com/show/4770/...cking-record-with-8429ghz-bulldozer-processor

 

[Svein]

What are the current obstacles from having one core 10 GHZ CPU processor?

Several, but I will just mention a non-obvious:

Take a clock running at 10GHz and assume a 50% duty cycle. Then each half period will be 50ps (pico-seconds). Since the speed of electrical signals in wires is about 200 000km/s, this is equivalent to 20cm/ns. Thus, 50ps corresponds to 1cm - which again means that after 1cm your clock will be 180° out of phase! Since the current size of an IC is about 1x1 cm, you already have to pay attention to your wire lengths at 4GHz (current technology), and this will be at least twice as hard at 10GHz.

When you get the chance, pick up a modern motherboard and look at the traces from the CPU to the memory. Some of them are "squiggly" in order to assure that all lines have the same length - and the memory clock is about 1GHz (yes, I know about 2166MHz memory, but that is DDR - double data rate).

One of the consequences of the line length problem is that fast interfaces have gone from parallel to serial (one data line matches its own length exactly).

 

[CWatters]

I'm not sure they have any crystal they could use to build an oscillator that fast (not sure about that though)

High frequency on chip oscillator phase locked to an external slower frequency?

 

[Vanadium 50]

High frequency on chip oscillator phase locked to an external slower frequency?

Just like you use today. Typically the external clock is around 100 MHz.

One could easily build a custom Z-80 that goes to 10 GHz. Fewer transistors means easier overclocking.

 

[Darryl]

A lot of the reasons for the limit of overall speed has to do with electrical impedance, that is resistance in proportion to frequency, and the power required to overcome that impedance. As the switching frequency increases you need more power to overcome the inductance and capacitance of the circuits, that actually translates to larger (and more power hungry) transistors, also it takes more time to overcome this increased impedance, the capacitance and inductance takes time to charge (and therefore switch).

The reason why CPU's get hotter when working at higher frequencies is due to the extra power to overcome the impedance.

 

[leright]

The primary problems are power dissipation and inductive/capacitive effects, as mentioned above.

To elaborate on the power dissipation problem, CMOS circuits in theory only conduct current and thus dissipate power while transistors are switching (there is some leakage though particularly due to quantum tunneling for modern circuits, so static power dissipation is still there). When they are either off or on and NOT switching they do not conduct current. While the frequency increases the time the IC spends switching becomes much higher, and thus power dissipation becomes higher.

 

[meBigGuy]

there is some leakage though particularly due to quantum tunneling for modern circuits, so static power dissipation is still there

I think you are underestimating the static current. And this isn't showing 14nm,

 

[leright]

I think you are underestimating the static current. And this isn't showing 14nm,

Which part of my comment made you think that? I am just saying that dynamic power consumption is one of the primary causes of power consumption and that is obviously related to clock frequency.

 

[Jeff Rosenbury]

Probably the biggest reason is lack of a market. All the technical problems can be overcome. I suspect they could build a 15 ps (PicoSecond) ECL (emitter coupled logic) set if anyone was willing to pay for it. However all the problems the other engineers listed still come back to bite us. The chip would need to be small. The timing would be difficult to manage. Thus the chip would lack some abilities we have come to expect in modern CPUs. And all of this would cost a lot more. Why pay more for less?

Video imaging has long been the driver of CPU advances. Once we developed good graphics drivers, there was less incentive to push ahead on speed. Add to this the enormous advances in programing algorithms and it's cheaper to use several processors than get too exotic on hardware.

Still, should there be a breakthrough in 3D circuitry, that might change. (3D circuitry shortens trace length, but dumping heat becomes a much bigger problem, particularly during manufacturing, but also in operation.) Cheap 3D circuits would likely lead to faster clock speeds.

 

[meBigGuy]

Which part of my comment made you think that? I am just saying that dynamic power consumption is one of the primary causes of power consumption and that is obviously related to clock frequency.

I'm saying that in modern processes static power dominates, that is, is the primary cause.

 

[leright]

I'm saying that in modern processes static power dominates, that is, is the primary cause.

Indeed. I don't debate this fact.