Engineering Verilog for a Simple Vending Machine

[christang_1023]

Homework Statement

A simple vending machine dispenses healthy muesli bars. It only accepts 50 cents and 1 dollar coins and a muesli bar costs 1 dollar. If an excess amount is entered, for example, 50 cents followed by one dollar, the transaction is rejected and all coins are returned.

Relevant Equations

Write the Verilog module for FSM using an active low asynchronous reset.

[CODE title="attempt to solutions"]module fsm(input clk, rst, fifty, onedollar,
output insert, dispense, reject);
reg [1:0] st;
wire [1:0] nst;
parameter ready = 2'b00, s1 = 2'b01, dispense = 2'b10, reject = 2'b11;
always@(posedge clk) begin
if ~rst st=ready;
else st=nst;
end
assign nst[0]=fifty&~onedollar&~st[1]|~st[1]&st[0]&(~fifty&onedollar|fifty&~onedollar);
assign nst[0]=~onedollar&fifty&~st[1]&~st[0]|~fifty&onedollar&~st[1]&st[0];
assign insert = ~st[1];
assign dispense = st[1]&~st[0];
assign reject = st[1]&st[0];
endmodule [/CODE]

I wonder if the way I write the combinational circuit, instead of using always block, is correct.

 

[jedishrfu]

Not really understanding your code but the notion of using the clock edge to change state looks right ie the always block seems like the right way to go.

Is there some edge case that you're worried about like no positive clock edge or like using the trailing clock pulse edge... ?

Perhaps @berkeman will have an idea here.