VHDL Code: Testing Equality of Vectors

AI Thread Summary
The discussion centers on a VHDL code snippet where the user attempts to compare specific bits of two 8-bit vectors, checkHR and checkMIN, against 4-bit vectors HRH and HRL. The user encounters an error indicating that the equality operator cannot be used with the operands in the current context. Other participants suggest that the code must be placed within a process and recommend posting the entire process for further analysis. They also request clarification on which variables are signals and which are ports to better diagnose the issue. The conversation emphasizes the importance of context and proper syntax in VHDL coding.
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Hi all, I have the following code:

if (checkHR(7 downto 4) = HRH) and (checkHR(3 downto 0) = HRL)
and (checkMIN(7 downto 4) = MINH) and (checkMIN(3 downto 0) = MINL) then

SECL <= "0000";
SECH <= "0000";
MINL <= "1000"; -- set to 8888 to notify alarm has been set
MINH <= "1000"; -- set to 8888 to notify alarm has been set
HRL <= "1000"; -- set to 8888 to notify alarm has been set
HRH <= "1000"; -- set to 8888 to notify alarm has been set

where checkHR and checkMIN are 8 bit vectors (7 downto 0)... and SECL, SECH, MINL, MINH, HRL, and HRH are all 4 bit vectors (3 downto 0).

What I'm trying to do is check to see if the first four bits of checkHR is equal to HRH.

Can someone tell me what's wrong? I'm getting the error: Line 74. = can not have such operands in this context.
 
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Did you put the code inside a process? You can only use the "if" statement inside a process.
 
Yes, it's in a process.
 
In the portion of code that you posted there is no syntax error. There must be some conflicting code somewhere else. You should post the whole process. Also tell us which of SECL, SECH, MINL, MINH, HRL, HRH, checkHR and checkMIN, are signals and which are ports.
 
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