- #1
AdrianRodz1
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- TL;DR Summary
- Can I reduce the Voltage Drop by decreasing the copper area on a plane layer?
I'm trying to maintain a spec requirement of less than 3% drop from farthest pin to closest pin from source.
I'used the entire layer for copper but my oart does not require such a large pour accept to handle high current.
So I'm considering there's a trade off that should meet inthe middle of reduced voltage drop w/out losing required capacitance.
I'used the entire layer for copper but my oart does not require such a large pour accept to handle high current.
So I'm considering there's a trade off that should meet inthe middle of reduced voltage drop w/out losing required capacitance.