I know very basically what pipe-lining is. My understanding is that the output from one "computing element" (usually a small set of instructions solving a simple task, such as say, finding a geometric mean) should flow immediately into the input of the following "computing element" where it is being used, instead of being stored somewhere in ram/cache and then retrieved again later. I've read that pipe-lining is easier to achieve (generally) with a RISC rather than a CISC. I regurgitated this to a friend of mine recently, and he asked why this would be so, and I couldn't give an answer. It feels right intuitively that RISC would be easier to do pipe-ling for than CISC...but in all honesty, I don't understand why. Could someone help me understand why? I already have a basic working understanding of the von Neumann architecture of CPU (ALU, PC, registers, control logic), but no real knowledge of real systems.