What is Nand gate: Definition and 15 Discussions

In digital electronics, a NAND gate (NOT-AND) is a logic gate which produces an output which is false only if all its inputs are true; thus its output is complement to that of an AND gate. A LOW (0) output results only if all the inputs to the gate are HIGH (1); if any input is LOW (0), a HIGH (1) output results. A NAND gate is made using transistors and junction diodes. By De Morgan's laws, a two-input NAND gate's logic may be expressed as AB=A+B, making a NAND gate equivalent to inverters followed by an OR gate.
The NAND gate is significant because any boolean function can be implemented by using a combination of NAND gates. This property is called functional completeness. It shares this property with the NOR gate. Digital systems employing certain logic circuits take advantage of NAND's functional completeness.
The function NAND(a1, a2, ..., an) is logically equivalent to NOT(a1 AND a2 AND ... AND an).
One way of expressing A NAND B is






A

B

¯




{\displaystyle {\overline {A\land B}}}
, where the symbol








{\displaystyle {\land }}
signifies AND and the bar signifies the negation of the expression under it: in essence, simply





¬
(
A

B
)




{\displaystyle {\displaystyle \neg (A\land B)}}
.
NAND gates with two or more inputs are available as integrated circuits in transistor-transistor logic, CMOS, and other logic families.

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  1. NYAME EPHRAIM

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  2. C

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  3. moenste

    How can a NAND gate be used as a NOT gate?

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  4. dwn

    Constructing a NAND Gate as Inverter: Troubleshooting Needed

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  5. I

    MHB Creating an inverter from a 2 input NAND gate

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  6. S

    Standard TTL 2-input NAND gate - open-collector/totem pole outputs

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  7. Y

    How does a NAND gate work using transistors?

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  8. I

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  9. N

    Implement ABC'D' using only one 2-input nand gate and one 3-input nor gate

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  10. D

    Pretty simple NAND gate question

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  11. T

    Draw C.(A(+)B)+ A.B Equation using Nand Gates

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  12. F

    Can a NAND gate be made without using a negative supply?

    If an AND gate is basically two switches in series, and an OR gate is two switches in parallel, how would you physicaly make a NAND/NOT/NOR gate? What is physically going on in the microchip which has these gates?
  13. C

    Is the implementation of the NAND gate unique?

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  14. D

    What happens when you place a NOT gate before and after a NAND gate

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