Logic Gates (NAND to AND Gates)

[desmond iking]

couldnt understand why the input is ( (XY)' (XY)' ) ' , IMO , it should be ((XY)' ) ' . because the 2nd logic gates receive (XY)' input from the first logic gates , and the second logic gates act as inverter for the first logic gates.

 

[jedishrfu]

I think they did that because the (XY)' is the input to the second gate and both inputs are tied together then they said (XY)'(XY)' and the second gates output is then ( (XY)' (XY)' ) ' which can be reduced to ( (XY)' ) ' and the double negative to simply XY so it shows that two NAND gates can be used to construct an AND gate.

 

[desmond iking]

I think they did that because the (XY)' is the input to the second gate and both inputs are tied together then they said (XY)'(XY)' and the second gates output is then ( (XY)' (XY)' ) ' which can be reduced to ( (XY)' ) ' and the double negative to simply XY so it shows that two NAND gates can be used to construct an AND gate.

Can I say the input is ((XY)' ) ' , which is also can be reduced to XY ?

 

[jedishrfu]

Yes, I believe that's right.

 

[alphy]

There are a few things to consider when discussing the input for NAND to AND gates. First, it's important to remember that NAND gates are essentially inverted AND gates. This means that the output of a NAND gate will be the opposite of what an AND gate would produce.

In this case, the input is ( (XY)' (XY)' ) ', which may seem confusing at first. However, when we break it down, we can see that the first (XY)' represents the output of the first NAND gate, which is then being inverted by the second NAND gate. The second (XY)' represents the output of the second NAND gate, which is then being inverted by the final NOT gate.

Essentially, the (XY)' input is being inverted twice, first by the second NAND gate and then by the final NOT gate, to produce the final output of the AND gate. This is necessary because, as mentioned earlier, NAND gates are inverted AND gates, so we need to invert the input twice to get the desired output.

In summary, the input for NAND to AND gates may seem unintuitive at first, but it is necessary in order to get the desired output. It is important to understand the properties of NAND gates and how they differ from AND gates in order to properly design and use logic gates in scientific research.