Need some advice on two's complement comparitor circuit

[Divergent13]

Normally I would ask this in the HW section but I think this would be better directed towards EE's.

I am trying to design a circuit for a design project that will take a 4-bit two's complement number (IE: A3A2A1A0) and output true if it is greater than another 4-bit two's complement number (IE: B3B2B1B0). I can make use of basic gates or full-adders.

I am trying to approach it using only basic gates because I would have to deal with overflow issues with full-adders. So what I was thinking is that I could compare the MSB first, and if it is 0 for A and 1 for B, then I know A > B and output 1.

If the MSB for A and B are both the same, then I need to look at the next bit over. Here, if the MSB's of A and B were 0, then I would output true if the next bit for A is 1 and B is 0. If the MSB's of A and B were 1, then I would output true if the next bit for A is 0 and B is 1. But then there is the case where the next bit for A and B are both the same, which would mean I have to dig to the next bit.

Basically, I am wondering how can I simplify this by not "digging" so deep into the bits and making use of so many gates. IE: I want to use reasonable engineering effort, even though Verilog will simplify it when I go to program on the GAL's, I want the paper design to be efficient.

Can anyone suggest a way I can infact use full-adders? We just got into them in lecture and I am still unsure how they work.

Thanks!

 

[dlgoff]

Too many gates? I think you could do it with 2 chips (quad 2-input NANDS) and 4 diodes.

 

[Theelectricchild]

You are going to have to make use of an adder/subtractor. Here are some necessary things to consider:

When A > B, what will be the MSB of the result A-B? What about B-A?

A-B will give you an MSB of 0, while B-A will give a 1.

http://en.wikipedia.org/wiki/Adder-subtracter

Basically, for the purposes of what you want to do, you will need to pay attention to the value of S3. As for dealing with overflow, I know it occurs when you take the last two carries and XOR them. Hopefully someone else can chime in on how to make your circuit "work" even when overflow occurs.

 

[Theelectricchild]

I was thinking about it more. You can deal with the overflow simply by XOR-ing C2 and C3, taking that result and XOR-ing it with the output of S3. I'll leave it to you to understand what that actually does. Good luck!

 

[rbj]

Normally I would ask this in the HW section but I think this would be better directed towards EE's.

I am trying to design a circuit for a design project that will take a 4-bit two's complement number (IE: A3A2A1A0) and output true if it is greater than another 4-bit two's complement number (IE: B3B2B1B0). I can make use of basic gates or full-adders.

I am trying to approach it using only basic gates because I would have to deal with overflow issues with full-adders. So what I was thinking is that I could compare the MSB first, and if it is 0 for A and 1 for B, then I know A > B and output 1.

If the MSB for A and B are both the same, then I need to look at the next bit over. Here, if the MSB's of A and B were 0, then I would output true if the next bit for A is 1 and B is 0. If the MSB's of A and B were 1, then I would output true if the next bit for A is 0 and B is 1. But then there is the case where the next bit for A and B are both the same, which would mean I have to dig to the next bit.

remember, that with 2's complement, the MSB is attached to a weigting that is negative, while for all the other bits, the weightings attached are positive powers or 2. so the logic about which is greater is reversed for the MSB.

Basically, I am wondering how can I simplify this by not "digging" so deep into the bits and making use of so many gates. IE: I want to use reasonable engineering effort, even though Verilog will simplify it when I go to program on the GAL's, I want the paper design to be efficient.

Can anyone suggest a way I can infact use full-adders? We just got into them in lecture and I am still unsure how they work.

one bit of full-adder is what you chain together to make a device that adds binary numbers. it is for bit #n and has three inputs and two outputs. rather than take time to explain, this Wikipedia article does a good job: http://en.wikipedia.org/wiki/Full_adder#Full_adder and http://en.wikipedia.org/wiki/Full_adder#Ripple_carry_adder .

comparing two numbers is the same as subtracting one from another and checking the result for negative (A<B), zero (A=B), and positive (B<A). we can subtract using an adder if the number being subtracted is first negated (X is converted to -X) and then added with the adder. in 2's complement, we negate a number by first inverting the bits (all the "1" bits become "0" bits and vise versa) and then add 1. this is true because

-X = (-1 - X) + 1

and -1 has a bit pattern with all bits set to 1 (imagine a base-2 odometer and backing up from 00000000 to 11111111, in base-10 it backs up to 999999 instead). when you subtract X from -1, there are no "borrows" and any 1 bit in X gets subtracted from a 1 and 0 is the result. likewize any 0 bit in X gets subtracted from 1 and 1 is the result.

now, with a chain of full adders, you can add that 1 easily by routing a 1 into the carry-in input of the least significant bit. that's how you turn an adder into a subtracter.

 

[Divergent13]

rbj, Theelectricchild, and dlgoff,

Thank you for your suggestions and the wealth of information. I do believe I have a working design using what was stated in this thread.

 

[Kenneth Mann]

May I suggest that the most direct and efficient answer to your problem would be to use an 8-variable K-Map. That would lead you directly to the answer, whatever your conditions may be. Most people seem to believe that these maps are limited to four or six variables, but I have included a tutorial that allows this to extend to eight to ten variables.

https://www.physicsforums.com/showthread.php?t=100628"