What dimension does process measure

[es1]

When someone says their transistors are a "90nm process"
(or similar) I always assumed they meant the minimum gate
length their fabrication process could produce.

But then while reading this:
http://www.intel.com/technology/silicon/65nm_technology.htm

I saw this:
"Intel's 65nm transistors have a reduced gate length of 35
nanometers and a gate oxide thickness of 1.2 nanometers."

Which seems to imply the process length does not imply
minimum gate length.

Does anybody know what feature of a transistor is measured
by the process dimension?

 

[berkeman]

It is the smallest feature size that can be imaged by the process. This would usually be the length of the gate metal, I believe, as you said. I don't understand the statement about the 35nm gate length in Intel's 65nm process either. I'll see if one of our chip designers knows what it means...

 

[chroot]

The process node name (e.g. "65 nm") is really a pretty vague indicator of actual feature sizes. The node name is mostly just a name given to a specific process so that different semiconductor designers and fabs can agree on their terminology -- they might as well have just called it "Freebird." The smallest feature sizes in "the 65 nm process" are actually quite a bit smaller than 65 nm, but 65 nm is a sort of "average" number used to describe the general size of features possible in the process.

- Warren

 

[chroot]

BTW, another couple of comments:

1) Modern MOSFETs are made with polysilicon gates, not metal gates.
2) The term "gate length" is a misnomer. You're probably referring to channel length.

- Warren

 

[berkeman]

Thanks for the info, Warren.

 

[es1]

A sort of 'average' feature size... I was not expecting that answer. :)
But I did expect it to be wrapped in a cloud of marketing.

I was able to find this
http://www.techweb.com/encyclopedia/defineterm.jhtml?term=process+technology
which more or less repeats what is here but offers some interesting historical data (basically the typical logarithmic type plots you see in chapter 1 of ee textbooks) and future predictions.

Thanks for the help!

 

[es1]

"The node name is mostly just a name given to a specific process so that different semiconductor designers and fabs can agree on their terminology"

I was thinking about this some more and thought how can it be both "they agree on their terminology" and "pretty vague indicator."

So I did some more google searches but with the new keyword "node." and found out this.

The process size refers to the half-pitch of the technology node. This is one half the average of the width and the space in between metal lines connecting bit cells in a DRAM if one were to implement a DRAM.

 

[chroot]

The process size refers to the half-pitch of the technology node. This is one half the average of the width and the space in between metal lines connecting bit cells in a DRAM if one were to implement a DRAM.

That's good info -- I wasn't aware that there was any specific measurement standard used. Do you have a reference where I could read more about this?

What about technologies that do not include digital blocks, e.g. sensor technologies? How does this kind of a measurement apply to them?

- Warren

 

[es1]

So I guess there are many measurements:

DRAM 1/2 pitch, ASIC 1/2 pitch, MPU printed gate length, MPU physical gate length, etc.

But, on a marketing slide, when you see X nm process they, apparently, mean the DRAM 1/2 pitch = X nm.

I did a google for (dram half pitch process node) and got tons of good stuff. But these links seem the most credible.

http://www.future-fab.com/documents.asp?grID=208&d_ID=2302
http://vlsicad.ucsd.edu/~abk/TALKS/michigan-020304.ppt

 

[chroot]

DRAM 1/2 pitch, ASIC 1/2 pitch, MPU printed gate length, MPU physical gate length, etc.

So my original assessment was correct: by itself, it's pretty much a meaningless number.

I'm just glad they didn't go the route of many other engineering standards, where they just keep tacking on 'ultra' and 'extra' and 'super' with each new generation.

It would be pretty hilarious to read Intel's press releases, though, when they excitedly announced their adoption of the brand new ultra-super-extra-super-extra-small process.

- Warren

 

[russ_watters]

You should see how they market air conditioners: "Standard", "high", "super", and "ultra" efficiency: http://www.trane.com/residential/products/AirConditioners.aspx

 

[es1]

Ya, I wondered why the fab houses never seemed bothered with that number. Now I know.

It would be funny to see the NFET, extreme edition, datasheet though. :)

 

[berkeman]

Sorry for the delay, but our resident analog chiphead just got back from vacation. Here's his answer when I asked him the OP question:

Decades ago, pretty much all the of the rules in a process were the
stated process size, with a few larger and a few smaller. e.g., 5um
width and space of polysilicon, the same for metal, the same for size
of contacts (vias); overlaps around contacts might be smaller, like 3um
for diffusion or 1um for metal. The electrical length for a 5um process
transistor would be about 4um typical, owing to side diffusion of the
source/drain dopant. This led some fabs, particularly lagging ones,
to call their process by the electrical length, to seem more
competitive.

In the mid 1980's, fabs experimented with "lambda rules" with drawn
metal and polysilicon having a minimum width and space of 2 lambda,
overlaps of 1 lambda. That worked pretty well for 2um processes
(lambda=1um) down to 1um processes (lambda=0.5um) or so. Designs
could be directly "shrunk" for new generations, changing only the bond
pads/pad ring. Once in a while fabs would develop a "faster" process,
where they managed to decrease the drawn transistor length, but left
all of the other rules the same (called a "go poly" process by some in
the mid 80's). As always, the various layers might get biased during
mask making, to optimize yield.

As dimension got smaller, manufacturing found that they could not decrease
some rules as fast as others. Polysilicon might be 0.35um width and space,
but metal width and space were larger. In evaluating a couple of vendors
while I was working at Nayna, we did a D flip-flop layout in each process,
and found as much as 40% area difference in processes called 1.2um by
their suppliers.

At this point, all the margin in all the rules is being used. At about 1.3um and
below, critical layers get optical pattern correction, where each shape on a layer
is examined in relationship to the other shapes. The tightly spaced shapes
are then modified to account for distortion during photolithography steps. The
distortion is caused by diffraction, which became significant as the dimensions
started appoaching the wavelength of light used for masking.

In the Intel article, it appears to me to be a 65nm lithography dimension,
with a 35nm electrical dimension. It really is more like a 35nm transistor,
since the post-process 65nm gate electrode is about 35nm, caused
by oxidation decreasing the width of the gate (oxide spacer technology, came
in to some extent starting around 1.6um, prolifereated by about 0.35um).

See

http://download.intel.com/technology/silicon/IRDS002_65nm_logic_process_100_percent.pdf

starting about page 21.

 

[chroot]

Thanks, berkeman.

Actually, that probably hints at the the clearest explanation I can come up with for the nomenclature.

Let's say you use a layout program and draw all your polygons on a one-lambda grid (i.e. a grid with 45 nm x 45 cells for a 90 nm process). If the grid spacing on your layout is 45 nm, then you are by definition working on a 90 nm process.

However, you don't really get nice little 45 nm x 45 nm squares on the silicon. The light used for the lithography diffracts around all the edges in your mask, and the lithography acts in some sense like a "low-pass filter." It softens all the corners and blurs all the edges of your polygons. Little squares become little circles, for example.

You have two options for dealing with this diffraction:

1) You can use optical proximity correction to pre-emphasize corners and other features, so the finished product more closely resembles your drawn polygons.

2) You can use the normally-detrimental effect to your advantage, creating polysilicon layers with gates much smaller than 90 nm.

In larger processes, diffraction is much less important, so if you drew a strip of polysilicon 1 um wide, you actually got a strip of polysilicon 1 um wide. With smaller processes, the relationship is much less straightforward.

- Warren

 

[es1]

A 40% difference in processes advertised to be the same. Wow, caveat emptor.

Thanks for the link to the slideshow. 1.72B transistors, 13nm lithographs! The mind boggles. Especially since they were able to improve yield while doing it.

BTW, I guess engineers didn't avoid the "ultra-super-extra-super-extra-small process." EUV (slide 7) -> Extreme ultraviolet lithography

 

[free_electron]

memory half-pitch

The International Technology Roadmap for Semiconductors refers to the process node number to describe the half-pitch of a NAND or DRAM memory cell extrapolated for a given year. Half-pitch being half the distance between adjacent lines of memory cells. Of course some companies are more aggressive and some are more conservative, so this number is only good in an average timing sense.

A logic-based 45 nm process or 65 nm process has nothing to do with this number; rather it is the timing (and of course, associated marketing) that is important.