Controller Area Network (CAN) bit stuffing

AI Thread Summary
Bit stuffing in Controller Area Network (CAN) is crucial for maintaining synchronization during message transmission, particularly due to the Non-Return-To-Zero (NRZ) encoding method used. In NRZ, long sequences of identical bits can lead to a lack of voltage transitions, which are necessary for the receiver to maintain clock synchronization and accurately interpret the data. To prevent this issue, bit stuffing introduces an additional bit after five consecutive bits of the same polarity, ensuring that transitions occur and allowing the receiver to identify bit boundaries. The absence of these transitions can cause the receiver to lose track of the timing, making it difficult to distinguish between individual bits. Understanding the role of transitions in NRZ is essential for effective communication in CAN systems.
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I was going through an article on CAN bus in Wikipedia & was stuck at the point where bit stuffing is explained. CAN is an asynchronous bus. They implement NRZ (Non-Return-To-Zero) encoding. To enable the receiver to correctly read the messages, continuous resynchronization is required.

Generally, in NRZ, a problem arises when there is a long sequence of 0s or 1s and the voltage level is maintained at the same value for a long time. This creates a problem on the receiving end because now, the clock synchronization is lost due to lack of any transitions and hence, it is difficult to determine the exact number of 0s or 1s in this sequence.

As per, http://www.softing.com/home/en/indu...re-can-bus/bit-encoding/bit-stuffing-rule.php
One characteristic of Non-Return-to-Zero code is that the signal provides no edges that can be used for resynchronization if transmitting a large number of consecutive bits with the same polarity. Therefore bit-stuffing is used to ensure synchronization of all bus nodes.
This means that during the transmission of a message, a maximum of five consecutive bits may have the same polarity. Then a bit is stuffed.

What I don’t understand is, why in NRZ, a consecutive 0’s & 1’s don’t provide edge? I assume edge means a transition. Am I right? Kindly explain me. Thanks in advance.
 
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In the following website, it is given that there won't be any transitions if there is large number of consecutive 0's or 1's. The bit boundaries can't be distinguished. So, the receiver clocks can't synchronise. But, what actually happens in receiver with each bit transition? And what happens if there is no transition? What happens when the bit boundaries can't be distinguished?

http://www.erg.abdn.ac.uk/~gorry/eg3567/phy-pages/nrz.html
 
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