ADC question(track and digital ramp)

[Bassalisk]

http://www.allaboutcircuits.com/vol_4/chpt_13/5.html

This counter thing.

Can somebody explain to me what does it mean to count up?

How does a device count "up" :D

I know what a clock does, it sends periodic pulses.

I believe the idea is, based on much impulses were counted, that would be the output.

I.E. if a voltage level of 5V has 125 impulses that is the binary word let's say 11111101?

 

[jedishrfu]

Just like when you count up after seeing a lightning strike 1001 1002 1003 boom
Storm is 3000 ft away.

The dac counts up to some value and then rollsmover to zero again thaats the saw tooth you in the article. Each count increments the output voltage a bit and then back to zero.

A countdown would work similarly except the voltage would decrease to zero and jump back to the max voltage.

 

[Bassalisk]

Just like when you count up after seeing a lightning strike 1001 1002 1003 boom
Storm is 3000 ft away.

The dac counts up to some value and then rollsmover to zero again thaats the saw tooth you in the article. Each count increments the output voltage a bit and then back to zero.

A countdown would work similarly except the voltage would decrease to zero and jump back to the max voltage.

Is this step always the same? How does it then convert that to binary word, is it by the principle I said?

 

[jim hardy]

let's make two simplifying assumptions:

that "free running" counter runs at 1 mhz, ie one clock pulse (count) per microsecond

and the DAC puts out one microvolt per count

obviously if analog input is a half volt
the counter will have to reach 500,000 counts and the DAC put out 1/2 volt
to trigger the comparator and start the next cycle.

that kind of DAC is a bit susceptible to noise on input. a negative "spike" will short-cycle it.
you'd low-pass the input before handing it to comparator.

http://www.onsemi.com/pub_link/Collateral/MC10E016-D.PDF

 

[Mike_In_Plano]

The counter looks like a 7416?, except that it is an 8 bit type while the 7416.. is 4 bit.

It looks as though the binary value of the counter increases on each clock tick until a clock tick comes in which the comparitor is low. Then the counter is set to zero via the load command and the eight low inputs. The next count would then be 00000001 (1) followed by 00000010 (2), etc.

For each of the binary values, the DAC will produce a corresponding analog value which is compared against the analog input. When the output of the DAC exceeds the analog input voltage, the comparitor goes low prompting the 8 bit latch (on the bottom right) to set it's output to the current binary value. Then the counter is set to zero agin on the next clock pulse.

 

[Bassalisk]

I need to digest this. Wait a minute.

That staircase, is that the output from the DAC?

 

[jim hardy]

""That staircase, is that the output from the DAC?"" yep


single chip DAC's abound these days. they're pretty smart.

http://www.linear.com/product/LTC1657

 

[Bassalisk]

""That staircase, is that the output from the DAC?"" yep.

single chip DAC's abound these days.

http://www.linear.com/product/LTC1657

But how... :D

How can that be output from DAC. Doesn't DAC, like R2R summation op amp has in-equal bits?

Don't we have steps like V/2; V/4; V/8 etc. How can you get that staircase?!

Where all are equal in between?

 

[jim hardy]

BASSALISK ignore this post!

[strike]i messed up. see my edit to post above yours. while you were typing...

""""That staircase, is that the output from the DAC?"" EDIT\

almost. It's what DAC would be putting out if it were told to output contents of its counter.
but it only does that when told to by comparator, see lines below.""

the counter counts up one count at a time. clock always increments least significant bit.[/strike]sorry my friend.

 

[jim hardy]

wow i got to slow down...staircase IS DAC output.

latch is done in the SRG.

remember the counter always increments its least significant bit so every step is same size. DAC follows along.

output of entire ADC block is parallel word from SRG representing size of input, and between comparator pulses iis latched at last value .

sorry, again

 

[Bassalisk]

wow i got to slow down...staircase IS DAC output.

latch is done in the SRG.

remember the counter always increments its least significant bit so every step is same size. DAC follows along.

output of entire ADC block is parallel word from SRG representing size of input, and between comparator pulses iis latched at last value .

sorry, again

aaaaaaaahaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa :D It increments by its LSB. Makes sense, I was assuming that but didn't know how it happens. No problem, I was solving some r2r problems(kid games really), sooo tired.

I will continue to study this tomorrow. I will tell you how it went on the exam. This all was very helpful.

Don't be sorry. Oh my God, you are my teacher here, along with other good fellows, do not apologize, I am the one who has to apologize for pursing the " I must know everything".

 

[Bassalisk]

To update my teachers!

Today I had an exam from digital electronics.

I did well in my opinion, just need to wait for the results. I even elaborated an error on the exam, and teaching assistants were telling me one thing but I was stubborn and when he called the professor, I was right!