Are 3.3V Supply Glitches on CPLD Safe for Reliable Performance?

[j777]

Hi,

I'm using a CPLD as an IO expander and I'm seeing +/- 200mV glitches with a 7ns period on the 3.3V supply (the CPLD uses this supply) when output pins are switched on and off. Based on the CPLD's datasheet the acceptable voltage range is 3.0V-3.6V. Are these glitches typical/safe or should I add some low value caps to cancel some of this noise?

 

[berkeman]

Power supply decoupling is key in fast circuits. I use one SMT 0.1uF decoupling cap for each Vdd input on an IC, placed on the top side of the PCB directly butted up next to the Vdd pin, with an immediate via to the Ground layer. If it's a 2-sided PCB, use ground pours on the top side to lower the Z and via to ground pours on the bottom side.

Also, when you are checking fast signals with an oscilliscope probe, it's important to use a Z-lead probe tip to lower the inductance of the ground return for the probe. If you don't have a standard Z-lead tip attachment, you can make your own with a small spring or even a paper clip.

 

[j777]

I have an SMT 0.1uF decoupling cap for each of the Vdd input pins as you have described. Is a supply glitch like this typical for digital outputs or should I begin to dig deeper?

 

[berkeman]

I have an SMT 0.1uF decoupling cap for each of the Vdd input pins as you have described. Is a supply glitch like this typical for digital outputs or should I begin to dig deeper?

It does sound a bit excessive to me, but I could be wrong. How many outputs are switching simultaneously to cause this glitch? Some FPGA/CPLD parts have limitations on how many outputs can switch simultaneously, if they are using a smaller package without lots of Vdd and ground pins. Maybe check your CPLD datasheet and app notes to see what they say about "simultaneous switching" of outputs to see if there are any limitations.

 

[j777]

I'll check the datasheet for simultaneous switching limitations but I'm only switching 8 simultaneously (for that 8-bit general purpose bus we were talking about in my last post).

 

[berkeman]

Interesting. Is there any chance that you have a timing violation when you are driving the bus, and are getting a temporary contention when you enable your output drivers? (Not likely -- I'm just throwing out ideas here.)

Are you using a Z-lead probe to check this glitch? It eliminates the ground wire of the probe, and instead provides a very short (<1cm) ground connection between the coaxial ground shield at the tip and a nearby ground point on your PCB.

 

[j777]

I am not using a Z-lead probe. How does this effect what I am seeing (I really don't know...I'm not trying to be smart)?

It is very possible that I have a timing violation when driving the bus...as you know this is my first go at this stuff. During a write (ie setting of outputs) the bus isn't driven by the CPLD though.

 

[j777]

Nevermind the z-lead probe question. I actually googled it and came up with a snippet from a pdf on your company's website. It sounds like this could be my problem (or lack of problem).

 

[j777]

Well I grounded my probe a little better and the glitch is at most +150mV/-110mV and I suspect I'd find that it's not even that much if I had a z-lead probe.

 

[j777]

I actually found some good information regarding supply decoupling for FPGAs and CPLDs on Altera's website that is helpful.

http://www.altera.com/support/devices/power/integrity/pow-integrity.html"

Based on this it looks like I should be using .01uF decoupling caps for the CPLD instead of .1uF. I'm going to make this change and see if it helps.

 

[berkeman]

Great work, Jason. That's how it works in the real world, BTW. I still like 0.1uF 0603 SMT decoupling caps, as long as the series L from the connection traces and vias is VERY low. But trying a mix of 0.1 and 0.01uF is a good avenue to pursue.