- #1

- 72

- 0

I had been wondering if this were possible for a long time. While working on my MS thesis at school, I learned about Phase Locked Loops for the first time. It took me weeks of curling up at night with H.&H.

I saw this great tutorial on the PF https://www.physicsforums.com/showthread.php?t=367280 on an induction heater and thats when it came together. In his tutorial, imsmoother writes a lot about the PLL theory, which helped me in my understanding. He configured his PLL so that it locks to the resonant frequency of his work coil + tank capacitor + work piece combination at about a 90° phase shift since he is measuring the voltage across the tank cap which adds -90° phase shift. He states that driving the transformer with this correct phase and frequency allows for Zero Voltage Switching of his transistors, increasing his efficiency. The power is varied by a variac on the mains, which is rectified to supply the Mosfet Half-Bridge that drives the transformer primary.

I was wondering about what happens when the work piece is changed and the inductance of the work coil changes, altering the resonant frequency of the LC. The PLL will easily adjust to the new frequency, but this means that the phase shift will change slightly. I wondered if it were possible to design a PLL that would maintain a constant phase shift over its entire lock range. I designed the circuit shown in attachment 1.

With the help of mathematica i found that the transfer function of the filter is

[itex]K_f = -\frac{(2 \pi \text{C2} \text{R2} s+1) (2 \pi \text{C1} s (\text{R1}+\text{R3})+1)}{2 \pi \text{R3} s (2 \pi \text{C1} \text{R1} s+1) (2 \pi \text{C2} \text{C3} \text{R2} s+\text{C2}+\text{C3})}[/itex]

This was still very mysterious to me until I actually built the circuit on my breadboard and saw it in operation. I programmed my Atmega328p to control a DAC, outputting a slow <1Hz Sine wave, plugged into a VCO of a different CD4046. I configured the VCO to produce audible frequencies and piped the output to a audio transformer + speaker so I could easily tell by ear when the PLL had locked. At first I didn't know what values to put, but I could tell that in the limit of R3→∞, C3→0, C2→C1 my transfer function would look like

[itex]K_f = \frac{2 \pi \text{C1} \text{R2} s+1}{2 \pi \text{C1} \text{R1} s+1}[/itex]

which is the same as the transfer function for the loop filter shown in the data sheet for the CD4046 and in

Convinced that my theory was sound, I began to think about changing my filters component values according to the theory I had read about, finally applying the information I had only barely understood in H.&H. To make this a lot more tactile, I created a LabVIEW VI that calculates and plots the response as you change each component (attachment 3). It was quite a brain teaser to figure out a way to make LabVIEW do this, and it was something I had wanted to know how to do for a long time.

I made one knob for each of the six passive components so I could watch the change in the Bode plot as I wiggle each of them. After some time I arrived at the configuration shown in the attachment. At this point I am wondering if what I am doing is correct. I have incorporated the gain of the phase detector, loop filter, and vco and plotted its open loop response, with phase margin shown. I adjusted the components until i found a nice point with 45° phase margin. I also plot the closed loop response on the right. From what I have shown, does it seem like my understanding of the PLL is correct? Will that minus sign come back to bite me? (the minus sign is not represented in the LabVIEW VI) It does seem to lock fine. I am wondering if I should try to move the phase margin frequency higher to get higher bandwidth, which I could do by increasing the overall gain and shifting the poles and zeros up higher.

So now another mysterious concept, Zero Voltage Switching. Less power loss and heating in your mosfets? Safer and more efficient power transfer? Sign me up. But how do you do it? I see like a hundred different proposed designs for ZVS full bridges and I'm not really understanding what is making them work. Some of them have extra inductors in the bridge, or extra inductors in series with the supply, or added on all over the place? How does the frequency of the drive signal affect the performance? How is the power varied? It seems that in most cases, diagonally opposite mosfets are turned on and off simultaneously, with a phase shift between the two diagonals to vary the duty cycle of the applied power. This takes advantage of the body diode of the power mosfets to allow freewheeling current to flow during the current reversal. How are these four drive signals and the variable phase difference between the two diagonal pairs controlled? If I were to use my PLL design to try to follow imsmoother's example of synchronizing my drive to some 90° shifted from the tank capacitor voltage, could I do that by making two PLLs that are nominally ±90° from the tank capacitor voltage, but then as I vary the phase adjust the two PLL followers will shift in opposite directions, leaving the overlapping period centered about the capacitor polarity switch? I'm wondering what method I would use to control the timing of the gate drive signals, and if an auxiliary L is needed anywhere. Parallel capacitances to the mosfets are not shown.

i used https://www.circuitlab.com/ and LaBVIEW to make these graphics

__The Art of Electronics__for me to even get the concept. I had never heard of a Bode plot, Poles, Zeros, Phase margin, or Laplace Transform before. Later on, while I was an intern, I used a Lead-Lag filter recommended my the manufacturer of an IC to stabilize its operation and in the process I learned that Lead-Lag compensation is ideal for stabilizing an amplifier with feedback.I saw this great tutorial on the PF https://www.physicsforums.com/showthread.php?t=367280 on an induction heater and thats when it came together. In his tutorial, imsmoother writes a lot about the PLL theory, which helped me in my understanding. He configured his PLL so that it locks to the resonant frequency of his work coil + tank capacitor + work piece combination at about a 90° phase shift since he is measuring the voltage across the tank cap which adds -90° phase shift. He states that driving the transformer with this correct phase and frequency allows for Zero Voltage Switching of his transistors, increasing his efficiency. The power is varied by a variac on the mains, which is rectified to supply the Mosfet Half-Bridge that drives the transformer primary.

I was wondering about what happens when the work piece is changed and the inductance of the work coil changes, altering the resonant frequency of the LC. The PLL will easily adjust to the new frequency, but this means that the phase shift will change slightly. I wondered if it were possible to design a PLL that would maintain a constant phase shift over its entire lock range. I designed the circuit shown in attachment 1.

With the help of mathematica i found that the transfer function of the filter is

[itex]K_f = -\frac{(2 \pi \text{C2} \text{R2} s+1) (2 \pi \text{C1} s (\text{R1}+\text{R3})+1)}{2 \pi \text{R3} s (2 \pi \text{C1} \text{R1} s+1) (2 \pi \text{C2} \text{C3} \text{R2} s+\text{C2}+\text{C3})}[/itex]

This was still very mysterious to me until I actually built the circuit on my breadboard and saw it in operation. I programmed my Atmega328p to control a DAC, outputting a slow <1Hz Sine wave, plugged into a VCO of a different CD4046. I configured the VCO to produce audible frequencies and piped the output to a audio transformer + speaker so I could easily tell by ear when the PLL had locked. At first I didn't know what values to put, but I could tell that in the limit of R3→∞, C3→0, C2→C1 my transfer function would look like

[itex]K_f = \frac{2 \pi \text{C1} \text{R2} s+1}{2 \pi \text{C1} \text{R1} s+1}[/itex]

which is the same as the transfer function for the loop filter shown in the data sheet for the CD4046 and in

__The Art of Electronics__except for an extra minus sign, and it worked. I was able to adjust the values a little bit more to get good performance from the loop. The minus sign turned out not to make a difference and I'm not entirely sure why. I think its because it just locks with a negative phase shift instead of a positive phase shift. imsmoother explicitly corrected for this minus sign by adding another inverting op amp follower. In my version, there is no DC path from the output of the op amp to its inverting input, therefore the voltage there will settle to almost exactly the same as the voltage applied to the non-inverting input. The only way for that to happen is if the XOR phase detector output to average out to the same value. It was very cool to adjust the phase setting (slowly) with a potentiometer while observing the two signals move relative to each other and simultaneously listening to the VCO output maintain a lock without introducing audible harmonic distortion.Convinced that my theory was sound, I began to think about changing my filters component values according to the theory I had read about, finally applying the information I had only barely understood in H.&H. To make this a lot more tactile, I created a LabVIEW VI that calculates and plots the response as you change each component (attachment 3). It was quite a brain teaser to figure out a way to make LabVIEW do this, and it was something I had wanted to know how to do for a long time.

I made one knob for each of the six passive components so I could watch the change in the Bode plot as I wiggle each of them. After some time I arrived at the configuration shown in the attachment. At this point I am wondering if what I am doing is correct. I have incorporated the gain of the phase detector, loop filter, and vco and plotted its open loop response, with phase margin shown. I adjusted the components until i found a nice point with 45° phase margin. I also plot the closed loop response on the right. From what I have shown, does it seem like my understanding of the PLL is correct? Will that minus sign come back to bite me? (the minus sign is not represented in the LabVIEW VI) It does seem to lock fine. I am wondering if I should try to move the phase margin frequency higher to get higher bandwidth, which I could do by increasing the overall gain and shifting the poles and zeros up higher.

So now another mysterious concept, Zero Voltage Switching. Less power loss and heating in your mosfets? Safer and more efficient power transfer? Sign me up. But how do you do it? I see like a hundred different proposed designs for ZVS full bridges and I'm not really understanding what is making them work. Some of them have extra inductors in the bridge, or extra inductors in series with the supply, or added on all over the place? How does the frequency of the drive signal affect the performance? How is the power varied? It seems that in most cases, diagonally opposite mosfets are turned on and off simultaneously, with a phase shift between the two diagonals to vary the duty cycle of the applied power. This takes advantage of the body diode of the power mosfets to allow freewheeling current to flow during the current reversal. How are these four drive signals and the variable phase difference between the two diagonal pairs controlled? If I were to use my PLL design to try to follow imsmoother's example of synchronizing my drive to some 90° shifted from the tank capacitor voltage, could I do that by making two PLLs that are nominally ±90° from the tank capacitor voltage, but then as I vary the phase adjust the two PLL followers will shift in opposite directions, leaving the overlapping period centered about the capacitor polarity switch? I'm wondering what method I would use to control the timing of the gate drive signals, and if an auxiliary L is needed anywhere. Parallel capacitances to the mosfets are not shown.

i used https://www.circuitlab.com/ and LaBVIEW to make these graphics