Building a CPU with Si JFETs: Fundamental Challenges?

[ZeroFunGame]

TL;DR

Would there be any fundamental reasoning (i.e. excluding cost, energy, and resources) that we could not build a modern day CPU using Si JFETs rather than Si CMOS? I realize the JFET device size would be huge, and the absences of enhancement mode JFETs may impact power consumption, but would there be any physical fundamental limits preventing the fabrication of a modern day CPU using only JFETs rather than CMOS?

Would there be any fundamental reasoning (i.e. excluding cost, energy, and resources) that we could not build a modern day CPU using Si JFETs rather than Si CMOS? I realize the JFET device size would be huge, and the absences of enhancement mode JFETs may impact power consumption, but would there be any physical fundamental limits preventing the fabrication of a CPU all using JFETs rather than CMOS?

 

[Svein]

You are confusing two different concepts. The equivalent of a n-channel JFET would be an N-channel MOSFET. CMOS is a technology based on the availability of both N-channel and P-channel MOSFETs.

N-channel at the bottom, P-channel at the top. The reason it can be designed to draw very little current is the fact that the threshold voltage for both devices can be designed in such a way the the two "never" conduct at the same time.

 

[ZeroFunGame]

Thanks Svein. I would like to clarify a bit in terms of comparing n-channel Si JFET ICs with Si CMOS ICs. It is possible to fabricate n-channel only circuits (for example, the Intel 80286 microprocessor had 134,000 transistors with just n-MOSFETs). Before the invention of Si MOSFETs, there existed Si JFETs. My question is, would there be any fundamental reasoning (i.e. excluding cost, energy, and resources) that we could not build a modern day CPU using Si JFETs rather than Si CMOS? JFETs would have huge gate lengths, but assuming we have a Si wafer of infinite size, and costs is not an issue, are there any fundamental challenges that limit a modern day CPU to be fabricated with Si n-channel JFETs?

 

[eq1]

I'm going to translate "modern day cpu" to digital device which can compute. I think if one does this then the answer is yes, one can make digital gates, and therefore more complex digital systems from JFETs. If nothing else one can do it RTL (resistor-transistor logic) [1] style. This totally ignores whether or not it's a good idea (I personally think it is not for a whole host of reasons) but one could do it if they chose to.

[1] https://en.wikipedia.org/wiki/Resistor–transistor_logic

 

[ZeroFunGame]

Would there be a fundamental clock speed limit due to the larger JFET gate length which may fundamentally limit Si JFET CPUs to run as fast as MOSFETs (assuming planar device structures - no FinFETs/GAA).

 

[eq1]

JFETs have high input capacitance and also a large miller effect compared to normal MOS, so it seems it must be slower, but honestly, I am not sure by how much and what the limiting factor would be as I haven't thought about JFETs in digital circuits before.

Even without the different switching characteristics, there has been a lot of thought put into how to construct a logic family from CMOS, so it will be very tough for JFETs to reach parity.

Out of curiosity, why do you ask?

 

[DaveE]

Theoretically, you can build a "modern cpu" out of any electronic switch; vacuum tubes, JFETS, BJTs, even diodes.
However, in the real world, "modern CPUs" are the creation of practical engineering, where things like tubes and JFETs were discarded long ago as not very practical for optimization of performance (size, speed, reliability, cost...).
So, I find your question a bit confusing. Like asking "Can you build a truck axle out of bamboo?"
Yes you can. But what is your real question?

 

[ZeroFunGame]

JFETs have high input capacitance and also a large miller effect compared to normal MOS

If JFETs are normally on, where would the input capacitance come from?

Even without the different switching characteristics, there has been a lot of thought put into how to construct a logic family from CMOS, so it will be very tough for JFETs to reach parity.

Out of curiosity, why do you ask?

It can be imagined that some semiconductor materials have not developed as far along as Si, and as such CMOS does not exist or may not be as robust to construct ICs. JFETs and BJTs are typically the go-to, hence trying to understand fundamental limitations of JFET ICs from reaching parity with CMOS.

 

[ZeroFunGame]

... where things like tubes and JFETs were discarded long ago as not very practical for optimization of performance (size, speed, reliability, cost...).

Size --> what prevents JFETs from scaling similar to MOSFETs?
Speed --> is this associated with size, hence capacitance, hence speed?
Reliability --> why would JFETs be not as reliable as MOSFETs? No need to deal with a gate oxide, or it's interface to the semiconductor. I'd imagine the oxide would break down first, where as JFET do not suffer from this.

So, I find your question a bit confusing. Like asking "Can you build a truck axle out of bamboo?"
Yes you can. But what is your real question?

In the scenario I am imagining, CMOS does not yet exist in a mature form for this semiconductor material, however, JFETs and BJTs do.

 

[Baluncore]

One problem with vacuum tube logic gates was the lack of a complementary P-version. There was also a problem with level converting the high anode output voltage down to the negative grid voltage of the next gate input.
The JFET shares that level shifting problem because it employs a reverse biased junction as an insulator between input and output.
To enable input and output voltages to operate between the same two supply rails an insulator is needed in the gate. That is a significant reason why the MOSFET is preferred over the JFET for integrated logic.

Multiple power supplies and level shifting systems are not needed with MOSFET logic circuits.

 

[eq1]

In the scenario I am imagining, CMOS does not yet exist in a mature form for this semiconductor material. However, JFETs and BJTs do.

You don't have to imagine that scenario. It happened. JFETs were productized in 1953, and the MOSFET didn't come around until 1959, and this is right as CPUs, as we would think of them today, were becoming a thing. So the industry could've chosen JFETs as the go-to technology but didn't.

I do think hypotheticals can be instructive but maybe we can turn this question on its head. Why do you think one should choose a JFET over a MOSFET for a digital circuit. If you were an engineer in the early 60s, when how to design a logic family was very much an open question, what would your case be?

 

[ZeroFunGame]

You don't have to imagine that scenario. It happened. JFETs were productized in 1953, and the MOSFET didn't come around until 1959, and this is right as CPUs, as we would think of them today, were becoming a thing. So the industry could've chosen JFETs as the go-to technology but didn't.

I do think hypotheticals can be instructive but maybe we can turn this question on its head. Why do you think one should choose a JFET over a MOSFET for a digital circuit. If you were an engineer in the early 60s, when how to design a logic family was very much an open question, what would your case be?

Imagine you are on the surface of Venus. Firstly, intrinsic carrier density would make Si unviable as a circuit element. Second, gate oxide reliability don't hold up to that temperature so you are left with JFET or BJT

If I may ask again:
Size --> what prevents JFETs from scaling similar to MOSFETs?
Speed --> is this associated with size, hence capacitance, hence speed?
Reliability --> why would JFETs be not as reliable as MOSFETs? No need to deal with a gate oxide, or it's interface to the semiconductor. I'd imagine the oxide would break down first, where as JFET do not suffer from this.

 

[Baluncore]

No need to deal with a gate oxide, or it's interface to the semiconductor. I'd imagine the oxide would break down first, where as JFET do not suffer from this.

OK. Design a NAND or NOR logic gate using JFETs. Use two power supply rails only, and specify common compatible input and output logic threshold voltages.

To speed up the logic transition time, minimise the signal transition voltage. Power is the product of current and voltage, so design your JFET circuit to operate on, preferably 6V or less.

Large Scale Integration is limited by thermal threshold changes due to power consumption. You will need to turn off internal bias currents logically, so the quiescent current at low clock rates should approach zero, leakage only.

I expect the majority of your circuit will be the voltage level changers needed to accommodate the internal JFET reverse biased junctions. Can you eliminate all resistors and replace them with JFETs?

How many masks for different layers of semiconductor and metalisation will you need for an integrated design?

Compare your design with insulated gate CMOS logic.

 

[ZeroFunGame]

OK. Design a NAND or NOR logic gate using JFETs. Use two power supply rails only, and specify common compatible input and output logic threshold voltages.

To speed up the logic transition time, minimise the signal transition voltage. Power is the product of current and voltage, so design your JFET circuit to operate on, preferably 6V or less.

Large Scale Integration is limited by thermal threshold changes due to power consumption. You will need to turn off internal bias currents logically, so the quiescent current at low clock rates should approach zero, leakage only.

I expect the majority of your circuit will be the voltage level changers needed to accommodate the internal JFET reverse biased junctions. Can you eliminate all resistors and replace them with JFETs?

How many masks for different layers of semiconductor and metalisation will you need for an integrated design?

Compare your design with insulated gate CMOS logic.

Im not arguing JFET over CMOS. However, I have not seen CMOS circuits that operate in Venusian temperatures due to 1) Si MOSFETs will be dominated by intrinsic carriers, 2) dielectric breakdown. Hence, non-Si IC without a gate dielectric (e.g. JFET/BJT)

 

[eq1]

Imagine you are on the surface of Venus. Firstly, intrinsic carrier density would make Si unviable as a circuit element. Second, gate oxide reliability don't hold up to that temperature so you are left with JFET or BJT

This doesn't really make sense to me. JFETs and MOSFETs can be made from the same things. Today both SiC JFETs and SiC MOSFETs can work under very high temperatures. In fact for those parts, the temperature rating is usually from the packaging, not the die. As for reliability, I don't have as much experience with JFETs but I would be willing to bet the designer is just trading one set of problems for another. I know of plenty of gotchas in JFET layout too.

If I may ask again:
Size --> what prevents JFETs from scaling similar to MOSFETs?
Speed --> is this associated with size, hence capacitance, hence speed?
Reliability --> why would JFETs be not as reliable as MOSFETs? No need to deal with a gate oxide, or it's interface to the semiconductor. I'd imagine the oxide would break down first, where as JFET do not suffer from this.

I'm interested to see what others say but I suspect there is no theoretical reason they can't scale to the speed and size of MOSFETs. Probably the only limitation is will. MOSFETs are off by default, and as Baluncore said, they don't require another rail which makes them much more convenient to work with from a practical standpoint. JFETs would have to bring something amazing to the table to overcome those limitations and for digital logic, I can't think of anything.

Your questions seem like they should be easily answered but they're just not specific enough. To borrow DaveE's analogy "Can you build a truck axle out of bamboo?" Sure, but what kind of truck? Are we talking semi or a tiny pickup? Etc. Etc.

For example, one may think an NFET is an NFET but there are a huge number of geometries. Even in just same planar process many are possible. I've seen whole textbooks on just the trade-offs of various FET layouts. And the layout has ramifications on reliability too. In my experience, more than the gate oxide. Earlier I said JFETs have a worse miller effect, but upon reflection that's only because the layouts I know of have a large gate to drain surface. Maybe there are better ones out there that minimize this? I don't know. One needs to pin a few design decisions down to make the questions answerable because it will start to bias the answer in one direction or the other.

 

[eq1]

Im not arguing JFET over CMOS. However, I have not seen CMOS circuits that operate in Venusian temperatures

Are you aware of JFETs circuits that have?

This team made a small SiC IC that withstood 500C.
https://smd-prod.s3.amazonaws.com/s...s/files/NASA_2016SMD_Report_final_highres.pdf
see page 11

 

[ZeroFunGame]

Are you aware of JFETs circuits that have?

https://sic.grc.nasa.gov/publications/technical/

 

[ZeroFunGame]

This doesn't really make sense to me. JFETs and MOSFETs can be made from the same things. Today both SiC JFETs and SiC MOSFETs can work under very high temperatures. In fact for those parts, the temperature rating is usually from the packaging, not the die. As for reliability, I don't have as much experience with JFETs but I would be willing to bet the designer is just trading one set of problems for another. I know of plenty of gotchas in JFET layout too.

One specific reason why MOSFETs may not be leveraged is because of its gate oxide, leading to unwanted interface states and charge traps that not only degrade performance but impact reliability if high temp swings and thermal shock is experienced. JFETs/BJTs avoid this issue since the gate oxide is not necessary for switching

 

[eq1]

https://sic.grc.nasa.gov/publications/technical/

Funny. That's the same team I linked to. I didn't know they made the circuit out of JFETs. Neither article said why they used them. But like I said, as one pins down design decisions it will bias the answer in one direction or the other. If surviving 1000C temperature swings is a requirement (which is definitely a non-standard requirement) then the inconvenience of designing a JFET logic gate probably outweighs the inconvenience of designing a gate oxide that doesn't die.

 

[ZeroFunGame]

Funny. That's the same team I linked to. I didn't know they made the circuit out of JFETs. Neither article said why they used them. But like I said, as one pins down design decisions it will bias the answer in one direction or the other. If surviving 1000C temperature swings is a requirement (which is definitely a non-standard requirement) then the inconvenience of designing a JFET logic gate probably outweighs the inconvenience of designing a gate oxide that doesn't die.

Which leads me to the original question of the post:

Would there be any fundamental reasoning (i.e. excluding cost, energy, and resources) that we could not build a modern day CPU using Si JFETs rather than Si CMOS? I realize the JFET device size would be huge, and the absences of enhancement mode JFETs may impact power consumption, but would there be any physical fundamental limits preventing the fabrication of a CPU all using JFETs rather than CMOS?

The answer to which is, so far, yes, you can, but due to the larger Miller capacitance, or device capacitance in general, switching speed will never reach parity with CMOS, but circuit complexity can. Is this a fair summary statement?

 

[eq1]

The answer to which is, so far, yes, you can, but due to the larger Miller capacitance, or device capacitance in general, switching speed will never reach parity with CMOS, but circuit complexity can. Is this a fair summary statement?

Flipping on the next page button on the link you sent shows this team has been building devices since at least 2002 and they have demonstrated many things, including FETs, above 500C. It's not clear why they picked JFETs for this demonstration but I suspect it is because JFETs require fewer processing steps, and their process is pretty exotic, so this would be a significant advantage.

My guess is these devices are large because of how they are fabricated and if they are large they will never reach the speed and density (basically by definition) of normal earth-only CMOS. Without the circuit density, it's not clear how they will match the complexity of today's CPUs. I'm sure they will eventually realize a basic CPU design but that's not parity in my mind.

 

[Baluncore]

Im not arguing JFET over CMOS.
However, I have not seen CMOS circuits that operate in Venusian temperatures due to 1) Si MOSFETs will be dominated by intrinsic carriers, 2) dielectric breakdown. Hence, non-Si IC without a gate dielectric (e.g. JFET/BJT)

You are clearly arguing JFET over CMOS. You are blaming the metal oxide insulator for reducing the die area needed by CMOS, which is disadvantaging your choice, the JFET loser. Technology is not a handicap race.

Rather than acknowledge the additional area needed on the die for the level converters and bias components essential with JFET logic gates, you have hypothesised a quite unrealistic Venusian environment. That is quite irrational. You need to design a JFET logic gate and then scale it down to discover the problems. Ask yourself why there are so few examples of JFETs used in logic circuits.

Insulated gates are never left floating. What have you got against oxide insulators that remain between the supply rails and can never have more than a few volts across them? I guess you must hold the same phobias against tantalum capacitors and dynamic memory.

 

[analogdesign]

I have some experience with this as I have implemented JFETs in a CMOS processes.

The answer to all your questions is: no, there is no theoretical limitation to implementing complex digital electronics only with JFETs but there are a lot of practical limitations.

In a given process technology the JFET would be larger in area (need to contact both sides of channel) and dissipate much more power (no complementary logic) than CMOS implemented in the same technology.

But again, there is no fundamental reason. There is also no real practical reason you would want to do so.

If you’re worried about high temperature operation you don’t even need to go to SiC or GaN to get pretty high supplies. You can use a BCD process and do it in CMOS.

Does that help?

 

[ormaaj]

You are clearly arguing JFET over CMOS. You are blaming the metal oxide insulator for reducing the die area needed by CMOS, which is disadvantaging your choice, the JFET loser.

It's apples and oranges kinda. On the most basic level a MOSFET is a JFET with one insulated gate.

Insulated gates are never left floating.

Floating gates are used extensively in domino and dynamic logic. Other niche uses like "zero-threshold" FETs probably find uses in digital designs rarely.

The answer to which is, so far, yes, you can, but due to the larger Miller capacitance, or device capacitance in general, switching speed will never reach parity with CMOS, but circuit complexity can. Is this a fair summary statement?

Well are the fastest InP HFETs these days faster than the fastest MESFET? Speed is probably the weakest argument there. JFETs do have larger Cgs but generally win in terms of transconductance / gm. There are many tricks to mitigate miller effect in CMOS and I'd expect similar for JFETs. The miller effect gets magnified further in a JFET since the gate is a varactor and capacitance goes up with voltage as the junction gets pinched.

OK. Design a NAND or NOR logic gate using JFETs. Use two power supply rails only, and specify common compatible input and output logic threshold voltages.

Yeah I brainstormed this a while ago. It's way hard to get any kind of useful complementary switching action using JFETs.

Can you eliminate all resistors and replace them with JFETs?

Probably. JFETs make useful active loads, current sources, and roughly linear VCRs (though usually such circuits do involve a resistor). The "lambda diode" is one that doesen't.