Calculating VDS(off) for Electronic Converters

[D44]

Hello

I'm trying to calculate V_DS(off) for the buck, boost and inverting converter.

All I have is V_in, V_out and duty cycle.

Am I correct in thinking V_DS(off) is the voltage across the FET?

I have no idea how to calculate this.

Thanks in advance.

 

[NascentOxygen]

V_DS is the usual way to designate the drain-source voltage. Beyond this, I think you are going to have to post a pic of the circuit if you want anyone to be able to help further.

 

[D44]

These are the 3 converter circuits.

Thanks

 

[berkeman]

Hello

I'm trying to calculate V_DS(off) for the buck, boost and inverting converter.

All I have is V_in, V_out and duty cycle.

Am I correct in thinking V_DS(off) is the voltage across the FET?

I have no idea how to calculate this.

Thanks in advance.

These are the 3 converter circuits.

Thanks

So for each of those topologies, you need to figure out what the voltage across the open FET will be during the Off part of the cycle. Like in the Buck circuit, what does the output voltage of the FET snap to when the FET is opened? What is the input voltage?

If you draw the switching waveforms (voltage and current) across the inductors in each circuit, that will help you figure this out.

 

[D44]

So if Vin = 20V, D = 30% and Vout = 6V, how do I go about drawing the waveforms? What exactly am I trying to find from this?

Thank you

 

[berkeman]

So if Vin = 20V, D = 30% and Vout = 6V, how do I go about drawing the waveforms? What exactly am I trying to find from this?

Thank you

You need to find the voltage waveform at the input to the inductor in the Buck circuit. That voltage alternates between the input voltage to the FET (when the FET is on), and what (when the FET snaps off)?

You should be able to use Google Images to find the waveforms, if your textbook doesn't have them. Your textbook does have them, doesn't it?

 

[D44]

These waveforms?

Alternates between input voltage and zero?

Assuming the waveforms are correct, what is it that I'm trying to work out from them? Am I meant to be integrating somehow?

 

[berkeman]

These waveforms?

Alternates between input voltage and zero?

Assuming the waveforms are correct, what is it that I'm trying to work out from them? Am I meant to be integrating somehow?

Good. Actually, the voltage at the input to the inductor in the Buck topology makes it down to -0.7V or so (a diode drop below ground). Do you see why that is?

So now you can answer the Vds(off) question for the Buck topology. The input to the FET is Vin when the output voltage is _____?

 

[D44]

I'm sorry, I don't see how it makes it down to -0.7V. Could you explain please?

The input to the FET is Vin when the output voltage is...Vout?! I really have no idea what I'm doing here...as you may tell!

 

[berkeman]

I'm sorry, I don't see how it makes it down to -0.7V. Could you explain please?

The input to the FET is Vin when the output voltage is...Vout?! I really have no idea what I'm doing here...as you may tell!

In a buck converter, when the input series switch (a FET in your case) opens up, the voltage at the input to the inductor snaps down. The "catch diode" or "flywheel diode" then supplies the inductor current for the "Off" part of the buck cycle.

What learning resources do you have for this course? How can you be given a problem set like this without even a basic introduction to how these circuits work? Something is strange here...

 

[D44]

You're telling me! :/

Poorly explained notes and a book that was a waste of money. Nowhere near enough content to help me with this.

I'm probably best trying to read up on this more because what you're saying means nothing to me.

Thanks for your time.

 

[berkeman]

You're telling me! :/

Poorly explained notes and a book that was a waste of money. Nowhere near enough content to help me with this.

I'm probably best trying to read up on this more because what you're saying means nothing to me.

Thanks for your time.

I googled DC-DC Converter Tutorial, and got lots of good hits:

http://www.google.com/search?source...tutorial&gs_upl=0l0l0l5078lllllllllll0&aqi=g5

Check out the one at the Maxim website near the top of the hit list. Also check out the tutorials at the National Semiconductor website about their Simple Switcher series of DC-DC converter control ICs.

 

[D44]

Thanks again, I appreciate it.

I'll have a good look and see where that gets me. I'll probably write on here in a day or 2 as I have work to be in next week and I don't like to leave things to the last minute.

 

[D44]

So if V_DS(off) is the voltage across the switch, surely for the buck and inverting circuits V_DS(off) would be the same as V_in?! But for the off part of the cycle, wouldn't it just be 0? For the inverting circuit, during the off part of the cycle, the inverter continues to provide current, but the switch is open, so there can't be any voltage across there either?

What is it that I'm failing to understand here?!

 

[D44]

It's the off subscript that's confusing me. But anyway, apparently this is the voltage across the switch during turn-on. So, that being the case, surely the voltage across the FET is just V_in?

 

[berkeman]

So if V_DS(off) is the voltage across the switch, surely for the buck and inverting circuits V_DS(off) would be the same as V_in?! But for the off part of the cycle, wouldn't it just be 0? For the inverting circuit, during the off part of the cycle, the inverter continues to provide current, but the switch is open, so there can't be any voltage across there either?

What is it that I'm failing to understand here?!

It's the off subscript that's confusing me. But anyway, apparently this is the voltage across the switch during turn-on. So, that being the case, surely the voltage across the FET is just V_in?

Just because there is no current through the FET when it is off, doesn't meant that there is no voltage across it. The FET looks like a high impedance when it is off.

So for the Buck converter, when the FET is off, it has Vin on its input side and ground (or -0.7V) on its output side going to the inductor and freewheel diode. So what is Vds(off) for the Buck topology?

For the Boost topology, think about what the output side of the FET does when the FET is off. What voltage do you get at the output side of the FET?

 

[D44]

So if V_in=20V, V_DS(off) is 20.7V? So when considering these circuits, ground is always -0.7V? I can't believe I've never heard/been told that...

The output side of the FET in the boost circuit would be V_out? So if V_out was 6V, V_DS(off) would be 14V?

 

[berkeman]

So if V_in=20V, V_DS(off) is 20.7V? So when considering these circuits, ground is always -0.7V? I can't believe I've never heard/been told that...

The output side of the FET in the boost circuit would be V_out? So if V_out was 6V, V_DS(off) would be 14V?

Ground is not at -0.7V. The cathode of the flywheel diode is connected to the inductor and the output of the FET. The anode of the diode is connected to ground. When the inductor current is supplied by the FET (when it is on), the voltage into the inductor is approximately Vin. When the FET shuts off, the input voltage to the inductor snaps down (similar to a "flyback" effect), and the diode "catches" the voltage at -0.7V. (If the diode were not there, the input voltage to the inductor would go a long way negative.) If you want to call the diode an "ideal diode" with 0V forward bias, then you could say that the input voltage to the inductor only makes it down to ground.

For the Boost converter, yes, the output FET voltage climbs to Vout (plus a diode drop...) when the FET is open.

 

[D44]

So it's just 20V? I understand now what you are saying about the diode. Thanks.

For the inverting circuit, the cathode of the diode is connected to the output of the FET and the inductor, with current being supplied to the load from the inductor. The anode is connected to the capacitor and load. What is the capacitor's role in this? Supplying the voltage? So the input to the FET is V_in and the output is 0.7V from the diode? Therefore V_DS(off)=19.3V?

Would you mind explaining the inverting circuit in a straight forward way please? So when the switch is closed, current flows through the inductor meaning... and when it is open...

Thanks

 

[berkeman]

So it's just 20V? I understand now what you are saying about the diode. Thanks.

For the inverting circuit, the cathode of the diode is connected to the output of the FET and the inductor, with current being supplied to the load from the inductor. The anode is connected to the capacitor and load. What is the capacitor's role in this? Supplying the voltage? So the input to the FET is V_in and the output is 0.7V from the diode? Therefore V_DS(off)=19.3V?

Would you mind explaining the inverting circuit in a straight forward way please? So when the switch is closed, current flows through the inductor meaning... and when it is open...

Thanks

I don't use the inverting topology much, but this is a reasonable tutorial on it:

http://www.simonbramble.co.uk/dc_dc...erter/inverting_dc_to_dc_converter_design.htm

The inverting topology uses the same basic principle as the other two. By connecting the inductor to the input supply for the ON time, you are ramping up a current in the inductor. When you turn the switch OFF, the current in the inductor cannot change to zero instantaneously, and the flyback voltage transient can be used to turn on a blocking diode for different purposes. In the Inverting topology, the diode turns on to pull current off of the - side of the output storage capacitor. This effectively pumps down the - side voltage of the cap with respect to ground. The duty cycle of the switch determines how fast or slow you pump that negative voltage down, and you would normally stabilize the duty cycle at whatever was needed to maintain the negative output voltage that you want.

The figure that you posted at the start of the thread for the Inverting topology converter is a little strange in that it does not label the - Vin point (and the "+" Vout point) as ground. That would be the more standard way of labeling the diagram, and is the way that the circuits in the link above are shown. So assuming that you show the bottom rail as ground in your figure, when the FET is ON, what voltage is the top of the inductor at? And when the FET shuts off, the voltage at the top of the inductor snaps down, and is caught at what voltage?

 

[D44]

So assuming that you show the bottom rail as ground in your figure, when the FET is ON, what voltage is the top of the inductor at? And when the FET shuts off, the voltage at the top of the inductor snaps down, and is caught at what voltage?

When the FET is on, the voltage at the top of the inductor would be V_in (20V in my case). When the FET shuts off, the voltage is caught at 0.7V. Therefore the voltage across the FET = 19.3V right?

 

[berkeman]

So assuming that you show the bottom rail as ground in your figure, when the FET is ON, what voltage is the top of the inductor at? And when the FET shuts off, the voltage at the top of the inductor snaps down, and is caught at what voltage?

When the FET is on, the voltage at the top of the inductor would be V_in (20V in my case). When the FET shuts off, the voltage is caught at 0.7V. Therefore the voltage across the FET = 19.3V right?

Not quite.

Remember, in the Inverting topology, you are pumping the negative rail down. Look to the right of the figure. What voltage are we pumping it down to?

 

[D44]

Infact, I have different numbers here for the boost and inverting circuits.

For the boost circuit:

Taking V_out = 12V, D = 25%, V_in = 9V. Therefore V_ds(off) = 9-12 = -3V. Is this correct, a negative answer?

For the inverting circuit:

Taking V_out = 12V, D = 25%, V_in = 36V.

 

[D44]

That could only be by 0.7V though, as that's all the diode allows through, right? So it would be 20.7V?

 

[D44]

Not 20.7, 36.7V

 

[berkeman]

Infact, I have different numbers here for the boost and inverting circuits.

For the boost circuit:

Taking V_out = 12V, D = 25%, V_in = 9V. Therefore V_ds(off) = 9-12 = -3V. Is this correct, a negative answer?

For the inverting circuit:

Taking V_out = 12V, D = 25%, V_in = 36V.

For the Boost circuit, the FET source is connected to ground. When the FET is open, what is the voltage on the anode of the diode (where the FET drain is connected)?

For the Inverting circuit, call the output Vout = -12V. So with an input voltage of Vin = 36 volts, what is the difference across the FET when it is off?

BTW, I would ask your instructor what they want you to use for the diode ON voltage. It will either be 0.6V, 0.7V. or 0V (for an "ideal diode").

 

[D44]

For the Boost circuit, when the FET is open, the voltage on the anode of the diode is V_in = 9V.

So for the inverting circuit, the voltage across the FET would be 48V? If this is the case, how is this so? I understand that current then flows the opposite way, through the reverse biased diode. I also understand that the charge is being pulled from the capacitor, but does the polarity only change because of the direction of the diode? With the diode being in place, I thought this would limit the voltage to 0.7V (or -0.7V), not -12V?

 

[D44]

I can assume the diode is operating ideally

 

[berkeman]

For the Boost circuit, when the FET is open, the voltage on the anode of the diode is V_in = 9V.

So for the inverting circuit, the voltage across the FET would be 48V? If this is the case, how is this so? I understand that current then flows the opposite way, through the reverse biased diode. I also understand that the charge is being pulled from the capacitor, but does the polarity only change because of the direction of the diode? With the diode being in place, I thought this would limit the voltage to 0.7V (or -0.7V), not -12V?

The voltage drop across the diode is 0.7V, so since the anode is at -12V, the cathode is at -12.7V. Your 48V number for Vds(off) for the inverting circuit looks good (assuming an ideal 0V diode drop).

 

[berkeman]

Can you post a summary your final answers for each circuit (including the Vin and Vout for each)?