If a capacitor is fully charged in a circuit, am I correct in saying that you can ignore that section of the circuit because no current goes through/leaves it?
I would still math it out, just because some circuits can do weird things, but most caps can handle upwards of a couple hundred volts, and if it's "fully charged" you're either saying: 1 it's in equilibrium with the voltage supply, or 2 it's at a higher voltage then your voltage supply, so current flows backwards, unless you have a huge supply.
IN the case of DC - and in a steady state - nothing changing, once the cap is charged, it "looks" like an open circuit. As soon as anything changes in time, the capacitor needs to be considered.
So when you say not fully charged - what do you mean, charged to it's maximum voltage - or you change something in the circuit like close a switch? For example - at Time 0 the cap is at 2 V and then something changes and the capacitor may charge to 6V... this is still a DC case, but the Capacitor needs to included in your analysis.
I'm pretty sure you'll want to use q=VC for it. Charge stored in the capacitor = voltage across the capacitor time its capacitance. If its not, sorry, I haven't analyzed DC circuited in forever. The only other equation coming to mind is the impedence, but that requires a frequency. Z=1/iwc in AC you use both, q for time dependent analysis, and z for complex analysis. Hope this helps, if not Google is your best friend, I'd look but I'm on my Droid now