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Creating a Moore state diagram

  • Thread starter Ald
  • Start date
Ald
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I have the following specification for a Synchronous Network, a sequence recognizer. I've done the Mealy state diagram and now have to do a Moore state diagram. I'm confused about how to go about the Moore version, I end up doing a Mealy.

I did the Mealy for this:

"Design a sequence detector with a single bit input line x and a single bit output line z. The output is to indicate (z=1) when the sequence 0110 has been detected on the input line x. The output is to detect overlapping sequences, and it is to immediately indicate when the sequence has been detected."

I now need to do a Moore state diagram, because I need to make z=1 for an entire clock cycle:

"Design a sequence detector with a single bit input line x and a single bit output line z. The output is to indicate (z=1 for an entire clock cycle) when the sequence 0110 has been detected on the input line x. The output is to detect overlapping sequences."

3. The Attempt at a Solution

Here is the state table for the Mealy state diagram

Present State Next State Output
A B A 0 0
B B D 0 0
D B F 0 0
F H A 1 0
H B D 0 0

Any help?
 

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