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rofln

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## Homework Statement

Complete the truth table for the following

http://forum.allaboutcircuits.com/image_cache/httpwww.freeimagehosting.netuploadsd537e2dd9a.jpg

## Homework Equations

JK Flip Flop Characteristic Table

D Flip Flop Characteristic Table

## The Attempt at a Solution

I understand how to make truth tables for logic circuits and I know the characteristic tables. But what is really stumping me is the AND gate that go to the JK Flip flop. It seems to me that whenever x and A are put together in the AND gate, it will always be zero except for the two entries where A and X are equal to one. I have the solutions manual and my answer is incorrect. It has 1's in row 2 and 4 but I have absolutely no idea how.

Here is what I have down just for the A column.

A B X A(t+1) B(t+1)

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

Any help and/or explanation would be very much appreciated, my final is on Wednesday and I want to get this topic rock solid in my head.

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