Decoder and register in Verilog

  • Thread starter Thread starter ACLerok
  • Start date Start date
  • Tags Tags
    Decoder
Click For Summary
SUMMARY

The discussion focuses on implementing a decoder in Verilog for a register file consisting of 16 instances. The goal is to create a decoder module that takes a 4-bit hexadecimal input representing the register number and outputs a 16-bit enable signal (enbl_sig) with a single bit set to 1, corresponding to the selected register. This approach ensures that only one register is written to at a time, utilizing a demultiplexor concept to manage the enable signals for each register instance.

PREREQUISITES
  • Understanding of Verilog programming language
  • Familiarity with digital logic concepts, specifically decoders and demultiplexors
  • Knowledge of binary and hexadecimal number systems
  • Experience with register file architecture in digital design
NEXT STEPS
  • Research Verilog decoder implementation techniques
  • Learn about demultiplexor design in digital circuits
  • Explore the use of 4-bit hexadecimal inputs in Verilog
  • Study register file design patterns and best practices
USEFUL FOR

Digital designers, Verilog programmers, and hardware engineers working on register file implementations and seeking to optimize data writing processes in FPGA or ASIC designs.

ACLerok
Messages
194
Reaction score
0
I'm trying to program the write action for a register file.
Basically I have 16 instances of a register file whose inputs are:

enbl - the enable signal
write_data - data to be written to register
clk - clock

and a single output, out, which is the value of the register.

The problem I'm having is developing a decoder that will set the enbl signal of only a single register to 1 for writing to the register so only 1 register will be written at any given time. All 16 registers will be of the same register module. I am thinking of creating a decoder module that receives the number of the register to be written, and then outputs a 16-bit binary number (called enbl_sig) that will be all 0's except for a single 1 in which the digit place corresponds to the register number to be written. Therefore I can just send enbl[0], enbl[1]... etc to each register instance. The register instance with enbl[.]=1 will be the one that will write the data to the register. Also, the received register number to write to will be received is a 4-bit hexadecimal number.

Sorry if this sounds confusing, but I don't know how else I would be able to do it. Does anyone have any suggestions or perhaps an easier method to accomplish this? I don't need the exact code, just the method of taking a 4-bit hexadecimal number and then outputting the desired 16-bit binary number. Thanks again.
 
Technology news on Phys.org
ACLerok said:
The problem I'm having is developing a decoder that will set the enbl signal of only a single register to 1 for writing to the register so only 1 register will be written at any given time. All 16 registers will be of the same register module. I am thinking of creating a decoder module that receives the number of the register to be written, and then outputs a 16-bit binary number (called enbl_sig) that will be all 0's except for a single 1 in which the digit place corresponds to the register number to be written. Therefore I can just send enbl[0], enbl[1]... etc to each register instance. The register instance with enbl[.]=1 will be the one that will write the data to the register. Also, the received register number to write to will be received is a 4-bit hexadecimal number.

It looks to me that what you are attempting to build is actually a demultiplexor.

I was following what you said until

The register instance with enbl[.]=1 will be the one that will write the data to the register. Also, the received register number to write to will be received is a 4-bit hexadecimal number.

I am having the most trouble here in terms of understanding what you want to do. Can you clarify a little bit regarding your "Received Register Number"?
 

Similar threads

  • · Replies 3 ·
Replies
3
Views
2K
  • · Replies 12 ·
Replies
12
Views
3K
  • · Replies 30 ·
2
Replies
30
Views
7K
  • Sticky
  • · Replies 13 ·
Replies
13
Views
8K
  • · Replies 10 ·
Replies
10
Views
4K
  • · Replies 7 ·
Replies
7
Views
4K
  • · Replies 1 ·
Replies
1
Views
2K
  • · Replies 5 ·
Replies
5
Views
4K
  • · Replies 3 ·
Replies
3
Views
2K
  • · Replies 5 ·
Replies
5
Views
2K