Designing a Clapp Oscillator: Distinguishing Negative Resistance & Tank Circuit

[dalarev]

Attached is an image of the clapp oscillator I am designing, DC bias not shown.

My question is, how can I distinguish between the part of the circuit acting as the negative resistance generator and that which functions as a tank circuit?

The resistor shown in the image is not part of the DC bias.

 

[vk6kro]

The coil and capacitors are the tank circuit and the FET is the negative resistance.

This is very similar to your last post
https://www.physicsforums.com/showthread.php?t=347677
so I have to wonder why are persisting with such unrealistic values of components?

 

[dalarev]

The coil and capacitors are the tank circuit and the FET is the negative resistance.

This is very similar to your last post
https://www.physicsforums.com/showthread.php?t=347677
so I have to wonder why are persisting with such unrealistic values of components?

Are you referring to the absence of transmission lines? They will be implemented in the design, but I fail to see other apparent inconsistencies with it.

My goal is to create subcircuits of the tank circuit/negative resistance generator separately, then use an oscillator probe available in the simulator which injects (initial) signals of certain frequency to test which one it will resonate at.

 

[berkeman]

Are you referring to the absence of transmission lines? They will be implemented in the design, but I fail to see other apparent inconsistencies with it.

I think he means unrealistic values like 1 Ohm // 1 pF.

 

[vk6kro]

Yes, that is right.

Modelling with values like 1nH, 1 pF and 1 ohm and with no DC bias values means the oscillator has no chance of working because the FET will have internal capacitances and inductances that are much greater than these values.

Why is there a 1 ohm resistor across the FET?

 

[dalarev]

Ahhh, hahaha, yes. My mistake; those parameters are only default values because I put together a schematic quickly just to be able to take a screenshot of it, to show the layout.

Though, in practice, both of my static capacitors do have values of 1 pF. My DC bias is not shown, but the NMOS allows a bias current of 0.5 mA. I keep omitting the DC bias circuit, though, because in the simulator I will use a block diagram of it.I was hoping someone could provide some good reading material on "true" negative resistance, meaning one which supplies power.