Differential amplifier with current mirror load

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Discussion Overview

The discussion revolves around the analysis of a differential amplifier with a current mirror load, focusing on the calculation of differential gain and common-mode gain. Participants explore various aspects of the circuit's behavior, including the effects of component values and configurations.

Discussion Character

  • Technical explanation
  • Mathematical reasoning
  • Debate/contested

Main Points Raised

  • One participant expresses uncertainty about their calculated differential gain and seeks assistance in deriving the common-mode gain.
  • Another participant suggests using the relationship between the currents through Q3 and Q4, along with the Vbe expressions, to compute the differential gain.
  • A different participant notes that finding Ic3 and Ic4 is straightforward due to the current mirror load but questions whether to include the output impedance in the differential gain calculation.
  • It is mentioned that the output resistances of Q3 and Q4 are large and may be ignored compared to the load resistances, but the base resistors should not be overlooked as they affect the voltage gain.
  • One participant highlights the importance of considering the single-ended output and explains how raising the input voltages affects the current flow and voltage drop at the output.

Areas of Agreement / Disagreement

Participants present multiple viewpoints on how to approach the calculations, particularly regarding the inclusion of certain resistances and the implications of single-ended output. No consensus is reached on the correct method for deriving the common-mode gain.

Contextual Notes

Participants express uncertainty about assumptions related to input base current and the effects of output impedance on gain calculations. The discussion reflects varying interpretations of the circuit's behavior under different conditions.

brewface
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The question and my attempt have been provided in the attachments...my problem is trying to find the differential gain, i have worked through to an answer but the answer I'm getting doesn't seem correct...also i have absolutely no idea how to derive the common-mode gain...any help is much appreciated
 

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You know the sum of currents thru Q3 and Q4 is constant = I. Use the expression i= isexp(Vbe/26mV) for Q3 and Q4. Vbe3 - Vbe4 = differential voltage input (except for the finite β which I'm ignoring (and maybe you're not supposed to). Now you can compute ic3 - ic4 and from that your differential gain.

The common-mode gain is usually the differential output divided by a change in the common input voltage, i.e. assuming Vin1 = Vin2. In that case, with transistors matched as stated, cm gain = 0. However, they might mean Vin1 ≠ Vin2 in which case the gain Vout/Vin, Vin = Vin1 - Vin2, will vary with the common-mode voltage (Vin1 + Vin2)/2. The cause here is the Early voltage of Q2 (∂I/∂Vce). I leave you to figure out the rest.
 
finding Ic3 and Ic4 are not difficult to do because of the current mirror load. you need the transconductance to find differential gain but I'm not sure whether or not to include the output impedance of the transistors.
 
The output resistances of Q3/Q4 are quite large at 100k versus the load resistances of Rc and RL (> 10x) and can probably be ignored since the resistance seen by the load cap is going to include a parallel combination of Rc and Ro.

What you can't ignore are the base resistors RB and you've done that by assuming there is no input base current. RB is almost equal to rPI so it's going to halve the voltage gain.

You'll have to assume an AC ground at the emitter of Q3 and use a hybrid-pi model of the transistor to get your equivalent half circuit and compute the gain from that.
 
brewface said:
...also i have absolutely no idea how to derive the common-mode gain...any help is much appreciated

I didn't notice the first time at looking at this that the output is single-ended. Raising vi1 and vi2 by a common voltage causes more current to flow through Q2. This current splits equally between Q3 and Q4 so that if the output is taken differentially, there is no change to the differential output voltage and common mode gain is zero. But single ended output is different. On one side of the differential pair, the increased current caused by higher emitter voltage on Q4 causes more current to flow through the output resistance of Q2 and this will cause a voltage drop at Vo. This gain is what you will need to compute.
 

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