So we've started digital logic in lectures and don't seem to understand some things about it. I've searched online but nobody seems to have explained some things.
D LATCH TIMING
Q1: Does LATCH response(as in truth tables) just mean that nothing will change?i.e its going to remember previous inputs?
Q2: In reference to the last row of inputs in the truth table for an RS Latch and Gated Latch, S and R are both 1 but the Q and Qbar are 0? Why is that? Should they not be remembering the 1 and 1 new inputs?
Q3: In reference to the Gated Latch, is the E(enable) input only to tell the circuit to remember the inputs of S and R? So the only time the circuit will remember what inputs its given is if the Enable Input is 1 aswell? Whats the actual purpose of it?
Q4: I have no idea what these timing diagrams are supposed to tell me? Are they just a visual representation of a truth table? Whats going on?