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Digital Logic - Latches

  1. Mar 30, 2016 #1
    1. The problem statement, all variables and given/known data
    So we've started digital logic in lectures and don't seem to understand some things about it. I've searched online but nobody seems to have explained some things.

    RS LATCH
    62bc75a187.jpg

    GATED LATCH
    4ace35ef85.png

    D LATCH TIMING
    4a262dd151.jpg

    Q1: Does LATCH response(as in truth tables) just mean that nothing will change?i.e its going to remember previous inputs?

    Q2: In reference to the last row of inputs in the truth table for an RS Latch and Gated Latch, S and R are both 1 but the Q and Qbar are 0? Why is that? Should they not be remembering the 1 and 1 new inputs?

    Q3: In reference to the Gated Latch, is the E(enable) input only to tell the circuit to remember the inputs of S and R? So the only time the circuit will remember what inputs its given is if the Enable Input is 1 aswell? Whats the actual purpose of it?

    Q4: I have no idea what these timing diagrams are supposed to tell me? Are they just a visual representation of a truth table? Whats going on?


    2. Relevant equations


    3. The attempt at a solution
     
  2. jcsd
  3. Mar 30, 2016 #2
    Ever wonder in a SR latch what the S and the R stand for??? Set and Reset. Once I realized that it made a lot more sense!

    Reset overides Set in this case. The only difference with the gated SR Latch is it has an Enable input as well.

    The inputs to the LATCH become S&E and R&E so if E is 0 what are you inputs? S=0 R=0 so you'll get whatever the previous value was :)

    A timing diagram shows you how the logic behaves when various inputs are given. From it you can tell things like whether the logic is rising edge or falling edge triggered. As you get into this more it will tell you about delay propogations as well.
     
  4. Mar 30, 2016 #3
    Q1: So basically. Reset rests all values back to the defaults?(Q default would be 0 and Qbar would be 1?).

    Q2: Following from that default logic above, if reset overides set then why is Qbar now 0?
     
  5. Mar 30, 2016 #4
    Q1) Yup
    Q2) It's considered an invalid set of inputs :)
     
  6. Mar 30, 2016 #5
    Awesomee. thanks so much. this cleared up so many things. :)
     
  7. Mar 30, 2016 #6
    No worries

    Check out http://www.cburch.com/logisim/ its a free simulator for digital logic. I found it quite helpful to set up circuits in there and see how they behave. Made it easier for me to wrap my head around things!
     
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