Doubt regarding PLL 565 free running frequency

[dexterdev]

Hi PF,
I am trying out LM565 PLL IC and designed the basic circuit for checking free running frequency f0 (2.5 KHz). I verified the f0 by not giving any input signal (input pin floating, should I GND it ??)

Now the problem is that while sweeping the frequencies up and down the free running frequency doesn't come inside the capture range.

What to do now?

-Devanand T

 

[NascentOxygen]

Hi PF,
I am trying out LM565 PLL IC and designed the basic circuit for checking free running frequency f0 (2.5 KHz). I verified the f0 by not giving any input signal (input pin floating, should I GND it ??)

I expect it should be grounded.

Now the problem is that while sweeping the frequencies up and down the free running frequency doesn't come inside the capture range.

How did you come to conclude this?

 

[dexterdev]

Because I designed the PLL with f0 = 2.5 KHz. I verified with the waveform through oscilloscope. But the capture range doesnot include the f0 when tried. I tried the experiment as in explained in

http://www.edaboard.com/thread283028.html#post1210267

f0 doesnot comes inside frequencies A and C

 

[jim hardy]

Read the section on loop filter and capture range.
If your loop is intentionally made slow, to give a narrow capture range, it'll be slow to lock and you may sweep across its whole capture range before it locks.

Start with values that give a wide capture range. And of course stop the sweep when lock is achieved.

So the output signal will have the same frequency and phase of input

actually it'll have a phase difference - that's how the phase detector develops an error signal for the VCO... probably ~90 degrees when locked at F₀

Watching it "lock in" first time is a real thrill. Be sure to use chop mode so it'll show true phase releation.

You might experiment with a LM567. It gives a logic output when lock is achieved that can light a LED for you.

 

[alphysicist]

Dear Devanand T,

Thank you for reaching out with your question about the LM565 PLL IC and its free running frequency. From your description, it seems that you have designed a basic circuit to test the free running frequency at 2.5 KHz. It is important to note that the free running frequency is the frequency at which the PLL will operate without any external input signal. In order to verify this frequency, it is recommended to ground the input pin to ensure that there is no external signal interfering with the results.

However, it appears that you are encountering an issue with the capture range while sweeping the frequencies up and down. This could be due to a number of factors such as incorrect circuit design, component values, or external interference. I would suggest double checking your circuit design and component values to ensure they are correct. Additionally, it may be helpful to troubleshoot for any potential external interference that could be affecting the results.

If the issue persists, I would recommend consulting the datasheet for the LM565 PLL IC and reaching out to the manufacturer for further assistance. They may be able to provide specific guidance for your circuit and help troubleshoot any potential issues.

I hope this helps and wish you the best of luck with your project.

Sincerely,