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Doubt regarding PLL 565 free running frequency

  1. Mar 13, 2013 #1
    Hi PF,
    I am trying out LM565 PLL IC and designed the basic circuit for checking free running frequency f0 (2.5 KHz). I verified the f0 by not giving any input signal (input pin floating, should I GND it ??)

    Now the problem is that while sweeping the frequencies up and down the free running frequency doesn't come inside the capture range. :confused:

    What to do now?

    -Devanand T
     
  2. jcsd
  3. Mar 14, 2013 #2

    NascentOxygen

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    Staff: Mentor

    I expect it should be grounded.
    How did you come to conclude this?
     
  4. Mar 14, 2013 #3
    Because I designed the PLL with f0 = 2.5 KHz. I verified with the waveform through oscilloscope. But the capture range doesnot include the f0 when tried. I tried the experiment as in explained in

    http://www.edaboard.com/thread283028.html#post1210267

    f0 doesnot comes inside frequencies A and C
     
  5. Mar 14, 2013 #4

    jim hardy

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    Science Advisor
    Gold Member
    2016 Award

    Read the section on loop filter and capture range.
    If your loop is intentionally made slow, to give a narrow capture range, it'll be slow to lock and you may sweep across its whole capture range before it locks.

    Start with values that give a wide capture range. And of course stop the sweep when lock is achieved.

    actually it'll have a phase difference - that's how the phase detector develops an error signal for the VCO.... probably ~90 degrees when locked at F0

    Watching it "lock in" first time is a real thrill. Be sure to use chop mode so it'll show true phase releation.

    You might experiment with a LM567. It gives a logic output when lock is achieved that can light a LED for you.
     
    Last edited: Mar 14, 2013
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