Electrical Engineering - Circuits - FET Transistor - Voltage Divider

In summary, the conversation discusses finding the voltage gain and output impedance for a small signal equivalent circuit. The solution involves using a technique to open the current source and inject a voltage at the output to find the current, which can then be used to calculate the output impedance. There is also a discussion about the correct configuration for the small signal circuit, and the differences between an unbypassed common-source configuration and a self-bias configuration. The correct expression for the output impedance is given and the use of an approximation is discussed. Finally, there is a mention of the value of V_{GS} not being provided and the difficulty in finding this value.
  • #1
GreenPrint
1,196
0

Homework Statement



Find the voltage gain [itex]A_{v}[/itex]

http://imageshack.com/a/img692/3117/qkwp.png

Homework Equations





The Attempt at a Solution



Is this the correct small signal equivalent?

http://imageshack.com/a/img203/5812/1yfe.png

I'm trying to find the output impedance [itex]Z_{O}[/itex] but can't seem to derive the correct output voltage?

Apparently
[itex]i_{O} = i_{D}(1 + g_{m}R_{S} + \frac{R_{D} + R_{S}}{r_{d}})[/itex]

I'm trying to solve for the output voltage using
[itex]A_{v} = \frac{v_{O}}{i_{O}} = \frac{i_{D}R_{D}}{i_{O}}[/itex]

I'm trying to find a expression in which [itex]i_{O}[/itex] is a function of [itex]i_{D}[/itex] and the resistors etc and try to get [itex]i_{D}[/itex] to cancel out so that way I can calculate the output impedance.

I have a feeling that my small signal circuit is incorrect.

Thanks for any help.
 
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  • #2
Your equiv. ckt. looks OK.

To find Zout, open all independent current sources, inject a voltage v at the output and record the current i. Then Zout = v/i.

So do that with your equiv. ckt.

To get the gain you need to compute g_m which is di/dv_gs for which you need the device's I vs. Vgs or I vs. Vds characteristic curves.
 
  • #3
Nifty FET link:

http://acpce.org/httpdocs/StudyMaterial-SE/FET-Basics-1.ppt#357,2,Types of Field Effect Transistors (The Classification)
 
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  • #4
Well when I open the current source [itex]Z = r_{d}||R_{D}[/itex] and the current is [itex]Z_{O} = \frac{v_{O}}{r_{d}||R_{D}}[/itex]

hm ok.
 
  • #5
GreenPrint said:
Well when I open the current source [itex]Z = r_{d}||R_{D}[/itex] and the current is [itex]Z_{O} = \frac{v_{O}}{r_{d}||R_{D}}[/itex]

hm ok.

Yes indeed.
 
  • #6
Pardon my intrusion, but it looks as though the source resistor isn't AC bypassed by a capacitor, so shouldn't your rd connect directly to the source terminal rather than ground?
 
  • #7
gneill is right.
So you (Greenprint) need to look again at Zo. Use the same technique I suggested in post 2. The change is not big but we do want to be correct.

@g: Thanks.
 
  • #8
Well in this case shouldn't this configuration be exactly the same as a self-bias JFET configuration with [itex]R_{S}[/itex] unbypassed, instead of [itex]R_{G}[/itex] we have [itex]R_{Th}[/itex]? I know that for a self-bias JFET configuration with [itex]R_{S}[/itex] unbypassed

[itex]Z_{O} = \frac{1 + g_{m}R_{S} + \frac{R_{S}}{r+{d}}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}R_{D}[/itex]

I believe the answer for the problem though is

[itex]\frac{R_{D}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}[/itex]

Why is there a difference?
 
  • #9
GreenPrint said:
Well in this case shouldn't this configuration be exactly the same as a self-bias JFET configuration with [itex]R_{S}[/itex] unbypassed, instead of [itex]R_{G}[/itex] we have [itex]R_{Th}[/itex]? I know that for a self-bias JFET configuration with [itex]R_{S}[/itex] unbypassed

[itex]Z_{O} = \frac{1 + g_{m}R_{S} + \frac{R_{S}}{r+{d}}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}R_{D}[/itex]

I believe the answer for the problem though is

[itex]\frac{R_{D}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}[/itex]

Why is there a difference?

Why do you think the answer is [itex]\frac{R_{D}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}[/itex]?

What would the answer be if rd were missing? If it were ∞ in other words?

Now look at both expressions and ask yourself what would the limit of each expression be as rd→∞?
 
  • #10
Well if [itex]r_{d}[/itex] is connect to the source then the small signal equivalent circuit for a voltage diver unbypassed [itex]R_{S}[/itex] is exactly the same as the small signal equivalent circuit for a self-bias configuration unbypassed [itex]R_{S}[/itex] if we treat [itex]R_{Th}[/itex] as [itex]R_{G}[/itex]

The formula for the output impedance [itex]Z_{O}[/itex] for a self-bias configuration unbypassed [itex]R_{S}[/itex] is

[itex]Z_{O} = \frac{1 + g_{m}R_{S} + \frac{R_{S}}{r_{d}}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}R_{D}[/itex]

if we take the limit

[itex]Z_{O} \stackrel{lim}{r_{d} → ∞} = \stackrel{lim}{r_{d} → ∞} \frac{1 + g_{m}R_{S} + \frac{R_{S}}{r_{d}}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}R_{D} = R_{D}[/itex]

Am I really suppose to go with this as the output impedance [itex]Z_{O}[/itex]?

The solutions manual from a previous version has this for the answer.

http://imageshack.com/a/img14/6652/3jn9.png

I know it could be a different problem but it looks like the same exact problem with a different value for [itex]r_{d}[/itex]
 
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  • #11
GreenPrint said:
Well in this case shouldn't this configuration be exactly the same as a self-bias JFET configuration with [itex]R_{S}[/itex] unbypassed, instead of [itex]R_{G}[/itex] we have [itex]R_{Th}[/itex]? I know that for a self-bias JFET configuration with [itex]R_{S}[/itex] unbypassed

[itex]Z_{O} = \frac{1 + g_{m}R_{S} + \frac{R_{S}}{r+{d}}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}R_{D}[/itex]

I believe the answer for the problem though is

[itex]\frac{R_{D}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}[/itex]

Why is there a difference?

If your expression for Zout for an unbypassed common-source config. is right then obviously someone decided that RS(gm + 1/rd) << 1. Why don't you plug in the numbers and verify that that approximation is valid.

And in fact if that approx. is valid then you can reduce the expression for Zout further, to a very simple function of just RD and rd.

EDIT: looking at your numbers, gmRs = 3.3 which is not << 1 so obviously your supposed answer can't be right. So stick with the unbypassed C/S expression.
 
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  • #12
Well isn't

[itex]g_{m} = \frac{2I_{DSS}}{V_{P}}(1 - \frac{V_{GS}}{V_{P}})[/itex]?

the only problem is that I don't know [itex]V_{GS}[/itex] and it's not given, and I'm not sure how to find this value. You see above it says "as before" but I have looked and they don't ever show how they got the value.
 
  • #13
GreenPrint said:
Well if [itex]r_{d}[/itex] is connect to the source then the small signal equivalent circuit for a voltage diver unbypassed [itex]R_{S}[/itex] is exactly the same as the small signal equivalent circuit for a self-bias configuration unbypassed [itex]R_{S}[/itex] if we treat [itex]R_{Th}[/itex] as [itex]R_{G}[/itex]

The formula for the output impedance [itex]Z_{O}[/itex] for a self-bias configuration unbypassed [itex]R_{S}[/itex] is

[itex]Z_{O} = \frac{1 + g_{m}R_{S} + \frac{R_{S}}{r_{d}}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}R_{D}[/itex]

if we take the limit

[itex]Z_{O} \stackrel{lim}{r_{d} → ∞} = \stackrel{lim}{r_{d} → ∞} \frac{1 + g_{m}R_{S} + \frac{R_{S}}{r_{d}}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}R_{D} = R_{D}[/itex]

Am I really suppose to go with this as the output impedance [itex]Z_{O}[/itex]?

The solutions manual from a previous version has this for the answer.

http://imageshack.com/a/img14/6652/3jn9.png

I know it could be a different problem but it looks like the same exact problem with a different value for [itex]r_{d}[/itex]

The purpose of taking limits is not to find Zo, or that Zo is RD.

You had two possible expressions for Zo. One way to tell which is correct is this:

You know what Zo would be if there were no rd; it would be just RD. So whatever expression you come up with, it must reduce to just RD if you take the limit of the expression when rd→∞.

The second expression's limit is [itex]\frac{R_{D}}{1 + g_{m}R_{S}}[/itex], which is not just RD.

The first expression's limit is just RD.

These two limits don't prove that the first expression is correct; they prove that the second expression is wrong. So, if you knew that the correct answer was one of the two expressions, taking these limits rules out the second one. This is just an aid, like checking units, to help you rule out a wrong result.

Now, if we substitute numerical values into the expressions, we get:

attachment.php?attachmentid=63750&d=1383854704.png


and:

attachment.php?attachmentid=63751&d=1383854704.png


The numerical evaluations are very different; the second is not even a very good approximation to the first.

Have you tried analyzing the circuit to determine Zo? rude man already suggested that you inject a test signal at the output node.

If you set up the KCL equation(s) and inject a 1 amp signal at the output node, the voltage there will be numerically equal to the impedance there. Do it symbolically and substitute numbers once you have a symbolic expression for Zo.
 

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  • #14
GreenPrint said:
Well isn't

[itex]g_{m} = \frac{2I_{DSS}}{V_{P}}(1 - \frac{V_{GS}}{V_{P}})[/itex]?

the only problem is that I don't know [itex]V_{GS}[/itex] and it's not given, and I'm not sure how to find this value. You see above it says "as before" but I have looked and they don't ever show how they got the value.

They must give you something abou the JFET. Like I_DSS and V_P? Where did you dig up your g_m and r_d?
?
 
  • #15
rude man said:
They must give you something abou the JFET. Like I_DSS and V_P? Where did you dig up your g_m and r_d?
?

Look at the first post. Idss, Vp and rd are given on the schematic. All GreenPrint has to do is look up the relevant formulas for Id vs. Vgs; then he can calculate the Q point for this circuit.
 
  • #16
GreenPrint said:
Well isn't

[itex]g_{m} = \frac{2I_{DSS}}{V_{P}}(1 - \frac{V_{GS}}{V_{P}})[/itex]?

the only problem is that I don't know [itex]V_{GS}[/itex] and it's not given, and I'm not sure how to find this value. You see above it says "as before" but I have looked and they don't ever show how they got the value.

You do have I_DSS and V_P. You can compute V_GS by using the standard JFET equation for i and equating i to the current thru R_S.
 
  • #17
So then [itex]Z_{O} = \frac{1}{R_{D}||(r_{d} + R_{S}})[/itex].
 
  • #18
Oh you mean find [itex]V_{GS}[/itex] using [itex]I_{D} = I_{DSS}(1 - \frac{V_{GS}}{V_{P}})^{2}[/itex]

equating the current [itex]I_{D}[/itex] as the current through [itex]R_{S}[/itex] some how?
 
  • #19
GreenPrint said:
So then [itex]Z_{O} = \frac{1}{R_{D}||(r_{d} + R_{S}})[/itex].

How did you get this? You know that gm has to be involved in there.
 
  • #20
I opened up the current source [itex]g_{m}V_{gs}[/itex] applied a test current of 1 A at [itex]V_{O}[/itex] and found [itex]V_{O}[/itex] using [itex]R_{D}[/itex] in parallel with [itex]r_{d}[/itex] in series with [itex]R_{s}[/itex]

See the attached picture
 

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  • #21
GreenPrint said:
So then [itex]Z_{O} = \frac{1}{R_{D}||(r_{d} + R_{S}})[/itex].

No. Why aren't you using your formua for the unbypassed R_S?
 
  • #22
GreenPrint said:
I opened up the current source [itex]g_{m}V_{gs}[/itex] applied a test current of 1 A at [itex]V_{O}[/itex] and found [itex]V_{O}[/itex] using [itex]R_{D}[/itex] in parallel with [itex]r_{d}[/itex] in series with [itex]R_{s}[/itex]

See the attached picture

You can't 'open up' the current source because v_gs is not zero if you apply a test voltage to the output to obtain Z_o. r_d affects v_s so then v_gs is affected too.
 
  • #23
GreenPrint said:
Oh you mean find [itex]V_{GS}[/itex] using [itex]I_{D} = I_{DSS}(1 - \frac{V_{GS}}{V_{P}})^{2}[/itex]

equating the current [itex]I_{D}[/itex] as the current through [itex]R_{S}[/itex] some how?

Exactly! Whaddaya mean, 'somehow'? You have I_D and you have R_S, so what do you suppose V_S = ? Like, volts = current times ohms? :smile:

Remember, V_GS = V_G - V_S and you can figure out V_G from your schematic diagram.
 
  • #24
but I thought I_D didn't go through R_S? but went through R_D?
 
  • #25
GreenPrint said:
but I thought I_D didn't go through R_S? but went through R_D?

Well, where do you think I_D goes? It has to return to ground and it's not going backwards thru the gate! Look at your schematic, post 1!

For a JFET, I_D = I_S.
 
  • #26
So then [itex]V_{GS}[/itex] is about -.974 V?The equation looks like a pain in the but to solve algebraically so i graphed it.
 
  • #27
rude man said:
No. Why aren't you using your formua for the unbypassed R_S?

That is indeed the correct formula?
 
  • #28
My answer key says [itex]Z_{O} = r_{d}||R_{D}[/itex] which I think is wrong?
 
  • #29
GreenPrint said:
That is indeed the correct formula?

Well, I solved for Zout using your equiv. ckt. but it's too tedious to figure out if my and your expressions are the same.

Where did you get your expression from? Why do you doubt that it's right?
 
  • #30
GreenPrint said:
My answer key says [itex]Z_{O} = r_{d}||R_{D}[/itex] which I think is wrong?
.

Yes, it's wrong.
It would be right if R_S were bypassed with a big capacitor.
 
  • #31
GreenPrint said:
So then [itex]V_{GS}[/itex] is about -.974 V?


The equation looks like a pain in the but to solve algebraically so i graphed it.

Why is it a pain? It's a simple quadratic in V_S.
 
  • #32
Oh you I think that was for the previous problem. Apparently he uses

[itex]\frac{R_{D}}{1 + g_{m}R_{s} + \frac{R_{D} + R_{S}}{r_{d}}}[/itex] is this wrong?

This is the reason why I think it's wrong.

Oh I mean it's just a lot of math so I just plugged it into my calculator and graphed it.

However in my book for a Self-Bias Configuration with Rs bypassed they get this

[itex]Z_{O} = \frac{1 + g_{m}R_{S} + \frac{R_{S}}{r+{d}}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}R_{D}[/itex]

and a self bias configuration with Rs bypassed has the same exact small signal equivalent circuit as the one in this problem. The only difference is that RG is RTh in this problem

but the electrician already said how it was wrong because when you take the limit as rd goes to infinity you don't get RD

weird I'm learning a lot from this lol
 
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  • #33
He doesn't show how he got the original expression but he does this see attached.

when i solved for VGS i got -0.974 V and gm = 5.403 mS

but this

[itex]Z_{O} = \frac{1 + g_{m}R_{S} + \frac{R_{S}}{r+{d}}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}R_{D}[/itex]

gives me 1730.826
 

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  • #34
GreenPrint said:
Oh you I think that was for the previous problem. Apparently he uses

[itex]\frac{R_{D}}{1 + g_{m}R_{s} + \frac{R_{D} + R_{S}}{r_{d}}}[/itex] is this wrong?

This is the reason why I think it's wrong.

Oh I mean it's just a lot of math so I just plugged it into my calculator and graphed it.

However in my book for a Self-Bias Configuration with Rs bypassed they get this

[itex]Z_{O} = \frac{1 + g_{m}R_{S} + \frac{R_{S}}{r+{d}}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}R_{D}[/itex]

and a self bias configuration with Rs bypassed has the same exact small signal equivalent circuit as the one in this problem. The only difference is that RG is RTh in this problem

but the electrician already said how it was wrong because when you take the limit as rd goes to infinity you don't get RD

weird I'm learning a lot from this lol

What "it" (above, in red) are you referring to?

I did not say this one is wrong:

[itex]Z_{O} = \frac{1 + g_{m}R_{S} + \frac{R_{S}}{r+{d}}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}R_{D}[/itex]

I said this one is wrong:

[itex]\frac{R_{D}}{1 + g_{m}R_{s} + \frac{R_{D} + R_{S}}{r_{d}}}[/itex]
 
  • #35
GreenPrint said:
He doesn't show how he got the original expression but he does this see attached.

when i solved for VGS i got -0.974 V and gm = 5.403 mS

but this

[itex]Z_{O} = \frac{1 + g_{m}R_{S} + \frac{R_{S}}{r+{d}}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}R_{D}[/itex]

gives me 1730.826

What values did you use for Rs, rd, and RD?

When I use these values, I get:

attachment.php?attachmentid=63757&d=1383882848.png
 

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<h2>1. What is a FET transistor?</h2><p>A FET (Field-Effect Transistor) is a type of transistor that uses an electric field to control the flow of current. It has three terminals: source, drain, and gate. The gate terminal controls the flow of current between the source and drain terminals.</p><h2>2. How does a FET transistor work?</h2><p>A FET transistor works by applying a voltage to the gate terminal, which creates an electric field that controls the flow of current between the source and drain terminals. When a positive voltage is applied to the gate, it attracts negatively charged electrons to the surface of the semiconductor material, creating a conductive channel between the source and drain. This allows current to flow through the transistor.</p><h2>3. What is a voltage divider?</h2><p>A voltage divider is a circuit that divides a voltage into smaller parts. It is typically made up of two resistors in series, with the output voltage taken from the connection between the two resistors. The output voltage is determined by the ratio of the two resistors, with the larger resistor producing a larger output voltage.</p><h2>4. How does a voltage divider work?</h2><p>A voltage divider works by using the principle of Ohm's law, which states that the current through a conductor between two points is directly proportional to the voltage across the two points. In a voltage divider, the two resistors in series create a voltage drop across each resistor, with the sum of the two voltage drops equal to the input voltage. The output voltage is then determined by the ratio of the two resistors.</p><h2>5. What are the applications of voltage dividers?</h2><p>Voltage dividers have many applications in electrical engineering, including as a level shifter, a sensor interface, a biasing circuit for transistors, and a feedback network in operational amplifiers. They are also commonly used in power supplies to provide a stable output voltage.</p>

1. What is a FET transistor?

A FET (Field-Effect Transistor) is a type of transistor that uses an electric field to control the flow of current. It has three terminals: source, drain, and gate. The gate terminal controls the flow of current between the source and drain terminals.

2. How does a FET transistor work?

A FET transistor works by applying a voltage to the gate terminal, which creates an electric field that controls the flow of current between the source and drain terminals. When a positive voltage is applied to the gate, it attracts negatively charged electrons to the surface of the semiconductor material, creating a conductive channel between the source and drain. This allows current to flow through the transistor.

3. What is a voltage divider?

A voltage divider is a circuit that divides a voltage into smaller parts. It is typically made up of two resistors in series, with the output voltage taken from the connection between the two resistors. The output voltage is determined by the ratio of the two resistors, with the larger resistor producing a larger output voltage.

4. How does a voltage divider work?

A voltage divider works by using the principle of Ohm's law, which states that the current through a conductor between two points is directly proportional to the voltage across the two points. In a voltage divider, the two resistors in series create a voltage drop across each resistor, with the sum of the two voltage drops equal to the input voltage. The output voltage is then determined by the ratio of the two resistors.

5. What are the applications of voltage dividers?

Voltage dividers have many applications in electrical engineering, including as a level shifter, a sensor interface, a biasing circuit for transistors, and a feedback network in operational amplifiers. They are also commonly used in power supplies to provide a stable output voltage.

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