1. Not finding help here? Sign up for a free 30min tutor trial with Chegg Tutors
    Dismiss Notice
Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

Electrical Engineering - Circuits - FET Transistor - Voltage Divider

  1. Nov 6, 2013 #1
    1. The problem statement, all variables and given/known data

    Find the voltage gain [itex]A_{v}[/itex]

    http://imageshack.com/a/img692/3117/qkwp.png [Broken]

    2. Relevant equations

    3. The attempt at a solution

    Is this the correct small signal equivalent?

    http://imageshack.com/a/img203/5812/1yfe.png [Broken]

    I'm trying to find the output impedance [itex]Z_{O}[/itex] but can't seem to derive the correct output voltage?

    [itex]i_{O} = i_{D}(1 + g_{m}R_{S} + \frac{R_{D} + R_{S}}{r_{d}})[/itex]

    I'm trying to solve for the output voltage using
    [itex]A_{v} = \frac{v_{O}}{i_{O}} = \frac{i_{D}R_{D}}{i_{O}}[/itex]

    I'm trying to find a expression in which [itex]i_{O}[/itex] is a function of [itex]i_{D}[/itex] and the resistors etc and try to get [itex]i_{D}[/itex] to cancel out so that way I can calculate the output impedance.

    I have a feeling that my small signal circuit is incorrect.

    Thanks for any help.
    Last edited by a moderator: May 6, 2017
  2. jcsd
  3. Nov 6, 2013 #2

    rude man

    User Avatar
    Homework Helper
    Gold Member

    Your equiv. ckt. looks OK.

    To find Zout, open all independent current sources, inject a voltage v at the output and record the current i. Then Zout = v/i.

    So do that with your equiv. ckt.

    To get the gain you need to compute g_m which is di/dv_gs for which you need the device's I vs. Vgs or I vs. Vds characteristic curves.
  4. Nov 6, 2013 #3

    rude man

    User Avatar
    Homework Helper
    Gold Member

    Nifty FET link:

    http://acpce.org/httpdocs/StudyMaterial-SE/FET-Basics-1.ppt#357,2,Types [Broken] of Field Effect Transistors (The Classification)
    Last edited by a moderator: May 6, 2017
  5. Nov 6, 2013 #4
    Well when I open the current source [itex]Z = r_{d}||R_{D}[/itex] and the current is [itex]Z_{O} = \frac{v_{O}}{r_{d}||R_{D}}[/itex]

    hm ok.
  6. Nov 6, 2013 #5

    rude man

    User Avatar
    Homework Helper
    Gold Member

    Yes indeed.
  7. Nov 6, 2013 #6


    User Avatar

    Staff: Mentor

    Pardon my intrusion, but it looks as though the source resistor isn't AC bypassed by a capacitor, so shouldn't your rd connect directly to the source terminal rather than ground?
  8. Nov 6, 2013 #7

    rude man

    User Avatar
    Homework Helper
    Gold Member

    gneill is right.
    So you (Greenprint) need to look again at Zo. Use the same technique I suggested in post 2. The change is not big but we do want to be correct.

    @g: Thanks.
  9. Nov 7, 2013 #8
    Well in this case shouldn't this configuration be exactly the same as a self-bias JFET configuration with [itex]R_{S}[/itex] unbypassed, instead of [itex]R_{G}[/itex] we have [itex]R_{Th}[/itex]? I know that for a self-bias JFET configuration with [itex]R_{S}[/itex] unbypassed

    [itex]Z_{O} = \frac{1 + g_{m}R_{S} + \frac{R_{S}}{r+{d}}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}R_{D}[/itex]

    I believe the answer for the problem though is

    [itex]\frac{R_{D}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}[/itex]

    Why is there a difference?
  10. Nov 7, 2013 #9
    Why do you think the answer is [itex]\frac{R_{D}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}[/itex]?

    What would the answer be if rd were missing? If it were ∞ in other words?

    Now look at both expressions and ask yourself what would the limit of each expression be as rd→∞?
  11. Nov 7, 2013 #10
    Well if [itex]r_{d}[/itex] is connect to the source then the small signal equivalent circuit for a voltage diver unbypassed [itex]R_{S}[/itex] is exactly the same as the small signal equivalent circuit for a self-bias configuration unbypassed [itex]R_{S}[/itex] if we treat [itex]R_{Th}[/itex] as [itex]R_{G}[/itex]

    The formula for the output impedance [itex]Z_{O}[/itex] for a self-bias configuration unbypassed [itex]R_{S}[/itex] is

    [itex]Z_{O} = \frac{1 + g_{m}R_{S} + \frac{R_{S}}{r_{d}}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}R_{D}[/itex]

    if we take the limit

    [itex]Z_{O} \stackrel{lim}{r_{d} → ∞} = \stackrel{lim}{r_{d} → ∞} \frac{1 + g_{m}R_{S} + \frac{R_{S}}{r_{d}}}{1 + g_{m}R_{S} + \frac{R_{S} + R_{D}}{r_{d}}}R_{D} = R_{D}[/itex]

    Am I really suppose to go with this as the output impedance [itex]Z_{O}[/itex]?

    The solutions manual from a previous version has this for the answer.

    http://imageshack.com/a/img14/6652/3jn9.png [Broken]

    I know it could be a different problem but it looks like the same exact problem with a different value for [itex]r_{d}[/itex]
    Last edited by a moderator: May 6, 2017
  12. Nov 7, 2013 #11

    rude man

    User Avatar
    Homework Helper
    Gold Member

    If your expression for Zout for an unbypassed common-source config. is right then obviously someone decided that RS(gm + 1/rd) << 1. Why don't you plug in the numbers and verify that that approximation is valid.

    And in fact if that approx. is valid then you can reduce the expression for Zout further, to a very simple function of just RD and rd.

    EDIT: looking at your numbers, gmRs = 3.3 which is not << 1 so obviously your supposed answer can't be right. So stick with the unbypassed C/S expression.
    Last edited: Nov 7, 2013
  13. Nov 7, 2013 #12
    Well isn't

    [itex]g_{m} = \frac{2I_{DSS}}{V_{P}}(1 - \frac{V_{GS}}{V_{P}})[/itex]?

    the only problem is that I don't know [itex]V_{GS}[/itex] and it's not given, and I'm not sure how to find this value. You see above it says "as before" but I have looked and they don't ever show how they got the value.
  14. Nov 7, 2013 #13
    The purpose of taking limits is not to find Zo, or that Zo is RD.

    You had two possible expressions for Zo. One way to tell which is correct is this:

    You know what Zo would be if there were no rd; it would be just RD. So whatever expression you come up with, it must reduce to just RD if you take the limit of the expression when rd→∞.

    The second expression's limit is [itex]\frac{R_{D}}{1 + g_{m}R_{S}}[/itex], which is not just RD.

    The first expression's limit is just RD.

    These two limits don't prove that the first expression is correct; they prove that the second expression is wrong. So, if you knew that the correct answer was one of the two expressions, taking these limits rules out the second one. This is just an aid, like checking units, to help you rule out a wrong result.

    Now, if we substitute numerical values into the expressions, we get:




    The numerical evaluations are very different; the second is not even a very good approximation to the first.

    Have you tried analyzing the circuit to determine Zo? rude man already suggested that you inject a test signal at the output node.

    If you set up the KCL equation(s) and inject a 1 amp signal at the output node, the voltage there will be numerically equal to the impedance there. Do it symbolically and substitute numbers once you have a symbolic expression for Zo.

    Attached Files:

    Last edited by a moderator: May 6, 2017
  15. Nov 7, 2013 #14

    rude man

    User Avatar
    Homework Helper
    Gold Member

    They must give you something abou the JFET. Like I_DSS and V_P? Where did you dig up your g_m and r_d?
  16. Nov 7, 2013 #15
    Look at the first post. Idss, Vp and rd are given on the schematic. All GreenPrint has to do is look up the relevant formulas for Id vs. Vgs; then he can calculate the Q point for this circuit.
  17. Nov 7, 2013 #16

    rude man

    User Avatar
    Homework Helper
    Gold Member

    You do have I_DSS and V_P. You can compute V_GS by using the standard JFET equation for i and equating i to the current thru R_S.
  18. Nov 7, 2013 #17
    So then [itex]Z_{O} = \frac{1}{R_{D}||(r_{d} + R_{S}})[/itex].
  19. Nov 7, 2013 #18
    Oh you mean find [itex]V_{GS}[/itex] using [itex]I_{D} = I_{DSS}(1 - \frac{V_{GS}}{V_{P}})^{2}[/itex]

    equating the current [itex]I_{D}[/itex] as the current through [itex]R_{S}[/itex] some how?
  20. Nov 7, 2013 #19
    How did you get this? You know that gm has to be involved in there.
  21. Nov 7, 2013 #20
    I opened up the current source [itex]g_{m}V_{gs}[/itex] applied a test current of 1 A at [itex]V_{O}[/itex] and found [itex]V_{O}[/itex] using [itex]R_{D}[/itex] in parallel with [itex]r_{d}[/itex] in series with [itex]R_{s}[/itex]

    See the attached picture

    Attached Files:

    Last edited: Nov 7, 2013
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook

Have something to add?
Draft saved Draft deleted

Similar Discussions: Electrical Engineering - Circuits - FET Transistor - Voltage Divider
  1. Electrical Engineering (Replies: 2)